# US 10,121,676 B2 · Interconnects fabricated by hydrofluorocarbon gas-assisted plasma etch

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- Number: US 10,121,676 B2
- Document ID: US10121676B2
- Status: Granted
- Kind: B2
- Application number: 15/847,369
- Filed: 2017-12-19
- Published: 2018-05-03
- Granted: 2018-11-06
- Earliest claimed: 2015-09-09
- Assignees: International Business Machines Corporation; Zeon Corporation
- Applicants: International Business Machines Corporation; Zeon Corporation
- Inventors: Robert L. Bruce; Eric A. Joseph; Joe Lee; Takefumi Suzuki
- Web page: https://patentgrep.com/patent/US10121676B2

## CPC

- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/43: Layouts of interconnections
- H10W 20/48: Insulating materials thereof
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

## Claims

### Claim 1

An integrated circuit, comprising:
a plurality of semiconductor devices; and
a plurality of conductive lines connecting the plurality of semiconductor devices, wherein a pitch of the plurality of conductive lines is approximately twenty-eight nanometers, wherein each of the plurality of conductive lines comprises:
a line of a conductive metal; and
a carbon-containing layer positioned directly between the conductive metal and a dielectric material.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive lines comprises copper.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive lines comprises a copper alloy.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive lines comprises gold.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive lines comprises nickel.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive lines comprises cobalt.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive lines comprises silver.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive lines comprises ruthenium.

### Claim 9

An integrated circuit, comprising:
a front end, comprising:
a semiconductor wafer; and
a plurality of semiconductor devices formed on the semiconductor wafer; and
a back end, comprising:
a dielectric layer;
a plurality of conductive lines formed in the dielectric layer, wherein a pattern density of the plurality of conductive lines has a pitch of approximately twenty-eight nanometers; and
a carbon-containing layer positioned directly between the dielectric layer and each conductive line of the plurality of conductive lines.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the plurality of conductive lines has a uniform profile.

### Claim 11 (depends on 9)

The integrated circuit of claim 9, wherein the back end further comprises:
a capping layer positioned directly between the dielectric layer and the front end.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the capping layer comprises silicon nitride.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, wherein the capping layer comprises silicon carbonitride.

### Claim 14 (depends on 11)

The integrated circuit of claim 11, wherein the capping layer comprises silicon oxycarbonitride.

### Claim 15 (depends on 11)

The integrated circuit of claim 11, wherein the dielectric layer comprises a low-k dielectric.

### Claim 16 (depends on 11)

The integrated circuit of claim 11, wherein the dielectric layer comprises an ultra-low-k dielectric.

### Claim 17 (depends on 11)

The integrated circuit of claim 11, wherein the dielectric layer comprises silicon dioxide.

### Claim 18

An integrated circuit, comprising:
a front end, comprising:
a semiconductor wafer; and
a plurality of semiconductor devices formed on the semiconductor wafer; and
a back end, comprising:
a dielectric layer;
a plurality of conductive lines formed in the dielectric layer, wherein the plurality of conductive lines has a uniform profile and a pattern density of the plurality of conductive lines has a pitch of approximately twenty-eight nanometers;
a carbon-containing layer positioned directly between the dielectric layer and each conductive line of the plurality of conductive lines; and
a capping layer positioned directly between the dielectric layer and the front end.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein the plurality of conductive lines comprises a plurality of interconnects for electrically connecting a plurality of semiconductor devices in the back end.