# US 10,121,675 B2 · Semiconductor device and a method for fabricating the same

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- Number: US 10,121,675 B2
- Document ID: US10121675B2
- Status: Granted
- Kind: B2
- Application number: 15/649,909
- Filed: 2017-07-14
- Published: 2018-07-05
- Granted: 2018-11-06
- Earliest claimed: 2016-12-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Ming Lee; Fu-Kai Yang; Mei-Yun Wang
- Web page: https://patentgrep.com/patent/US10121675B2

## CPC

- H10P 50/283: {by chemical means}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate;
source/drain epitaxial layers disposed between two adjacent gate structures; and
an etching-stop layer (ESL) covering the source/drain epitaxial layers;
forming an opening in the ILD layer by etching;
forming a dielectric filling layer in the opening;
removing, by using wet etching, the ILD layer disposed above the source/drain epitaxial layers;
removing the ESL disposed on the source/drain epitaxial layers, thereby at least partially exposing the source/drain epitaxial layers; and
forming a conductive material over the exposed source/drain epitaxial layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein dielectric materials for the ESL, the cap insulating layer and the dielectric filling layer are different from a dielectric material for the ILD layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the dielectric material for the ESL is same as the dielectric material for the dielectric filling layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
the ESL is made of at least one selected from the group consisting of SiN and SiCN,
the cap insulating layer is made of at least one selected from the group consisting of SiN and SiON,
the dielectric filling layer is made of at least one selected from the group consisting of SiN and SiCN, and
the ILD layer is made of SiO2.

### Claim 5 (depends on 4)

The method of claim 4, wherein:
each of the gate structures further includes sidewalls spacers formed on opposing sides of the metal gate, and
the sidewall spacers are made of at least one selected from the group consisting of SiCN and SiOCN.

### Claim 6 (depends on 1)

The method of claim 1, wherein the wet etching utilizes dilute HF.

### Claim 7 (depends on 1)

The method of claim 1, wherein in forming the opening, the cap insulating layer is partially removed and the dielectric filling layer is formed on a portion of the cap insulating layer where the cap insulating layer is partially removed.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
each of the gate structures further includes sidewalls spacers formed on opposing sides of the metal gate, and
in forming the opening, the ESL and the sidewall spacers are partially removed and the dielectric filling layer is formed in contact with the sidewall spacers.

### Claim 9 (depends on 1)

The method of claim 1, wherein the opening is formed by dry etching using a hard mask pattern including a TiN layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein:
after the opening is formed, part of the ILD layer remains under the opening, and
the dielectric filling layer is formed in the opening above the remaining ILD layer.

### Claim 11

A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
first to fourth gate structures, each having a metal gate, sidewall spacers disposed on opposing sides of the metal gate and a cap insulating layer disposed over the metal gate, the first to fourth gate structures being arranged in this order along a first direction;
a first source/drain (S/D) epitaxial layer and a second S/D epitaxial layer, both disposed between the second gate structure and the third gate structure; and
an etching-stop layer (ESL) covering the first and second S/D epitaxial layers;
forming a first opening in the ILD layer by etching over an area including a region between the first and second S/D epitaxial layer;
forming a dielectric filling layer in the first opening;
removing, by using wet etching, the ILD layer disposed above the first and second S/D epitaxial layers, thereby forming a second opening and a third opening, respectively, and the ILD layer disposed between the first gate structure and the second gate structure, thereby forming a fourth opening;
removing the ESL disposed on the first and second S/D epitaxial layers, thereby at least partially exposing the first and second S/D epitaxial layers; and
forming a conductive material over the exposed first and second S/D epitaxial layers, thereby forming a first S/D contact on the first S/D epitaxial layer and a second S/D contact on the second S/D epitaxial layer, and in the fourth opening, thereby forming a contact bar.

### Claim 12 (depends on 11)

The method of claim 11, wherein dielectric materials for the ESL, the cap insulating layer, the sidewall spacers and the dielectric filling layer are different from a dielectric material for the ILD layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
the ESL is made of at least one selected from the group consisting of SiN and SiCN,
the cap insulating layer is made of at least one selected from the group consisting of SiN and SiON,
the sidewall spacers are made of at least one selected from the group consisting of SiCN and SiOCN,
the dielectric filling layer is made of at least one selected from the group consisting of SiN and SiCN, and
the ILD layer is made of SiO2.

### Claim 14 (depends on 11)

The method of claim 11, wherein the wet etching utilizes dilute HF.

### Claim 15 (depends on 11)

The method of claim 11, wherein in forming the first opening, the cap insulating layer is partially removed and the dielectric filling layer is formed on a removed portion of the cap insulating layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein, in forming the first opening, the ESL and the sidewall spacers of the second and third gate structures are partially removed and the dielectric filling layer is formed in contact with the sidewall spacers of the second and third gate structures.

### Claim 17 (depends on 11)

The method of claim 11, wherein the first opening is formed by dry etching using a hard mask pattern including a TiN layer.

### Claim 18 (depends on 11)

The method of claim 11, wherein:
after the first opening is formed, part of the ILD layer remains under the first opening, and
the dielectric filling layer is formed in the first opening above the remaining ILD layer.

### Claim 19

A method of manufacturing a semiconductor device, the method comprising:
forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
a first gate structure and a second gate structure, each of which includes a metal gate and a cap insulating layer disposed over the metal gate;
source/drain epitaxial layers disposed between the first and second gate structures; and
an etching-stop layer (ESL) covering the source/drain epitaxial layers;
forming openings in the ILD layer by etching, the openings partially overlapping source/drain epitaxial layers, in plan view;
forming a dielectric filling layer in the openings;
removing, by using wet etching, the ILD layer disposed above the source/drain epitaxial layers;
removing the ESL disposed on the source/drain epitaxial layers, thereby at least partially exposing the source/drain epitaxial layers; and
forming a conductive material over the exposed source/drain epitaxial layers.

### Claim 20 (depends on 19)

The method of claim 19, wherein one of the openings partially overlaps two of the source/drain epitaxial layers.