# US 10,121,670 B2 · Methods of fabricating semiconductor structures

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- Number: US 10,121,670 B2
- Document ID: US10121670B2
- Status: Granted
- Kind: B2
- Application number: 15/678,747
- Filed: 2017-08-16
- Published: 2017-12-21
- Granted: 2018-11-06
- Earliest claimed: 2014-10-07
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John D. Hopkins
- Web page: https://patentgrep.com/patent/US10121670B2

## CPC

- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.

## Claims

### Claim 1

A method of fabricating a semiconductor structure, the method comprising:
forming at least one opening through a stack of alternating tier dielectric materials and tier control gate materials;
removing lateral portions of each of the tier control gate materials to form control gate recesses;
forming a charge blocking material on exposed surfaces of the tier dielectric materials and the tier control gate materials in the at least one opening, the charge blocking material comprising a charge trapping portion;
filling the control gate recesses with a charge storage material;
removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material; and
filling the air gaps with a dielectric material, wherein filling the air gaps comprises forming a silicon oxide material in the air gaps and wherein forming a silicon oxide material in the air gaps comprises,
forming a low quality silicon oxide material in the air gaps, and
converting the low quality silicon oxide material to a higher quality silicon oxide material.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming a charge blocking material comprises:
forming a first dielectric material on the exposed surfaces of the tier control gate materials in the control gate recesses;
forming a second dielectric material on the first dielectric material and on the exposed surfaces of the tier dielectric materials, the second dielectric material comprising a charge trapping material; and
conformally forming a third dielectric material over the second dielectric material.

### Claim 3 (depends on 1)

The method of claim 1, wherein removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material comprises:
selectively removing the charge trapping portion disposed horizontally between the charge storage material and the adjacent tier dielectric material without substantially removing portions of the charge blocking material disposed vertically between the charge storage material and the adjacent tier control gate material.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming a silicon oxide material in the air gaps comprises forming the silicon oxide material using a process selected from the group consisting of an in situ steam generation (ISSG) process, an atomic layer deposition (ALD) process, a furnace growth (diffusion) process, and combinations thereof.

### Claim 5 (depends on 1)

The method of claim 1, wherein filling the control gate recesses with a charge storage material comprises forming the charge storage material laterally adjacent to the charge blocking material.

### Claim 6 (depends on 1)

The method of claim 1, further comprising extending the at least one opening through a control gate material of a select device, an oxide material underlying the control gate material of the select device, and into a portion of a source.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming a tunnel dielectric material conformally on sidewalls of the at least one opening.

### Claim 8 (depends on 7)

The method of claim 7, further comprising, after forming the tunnel dielectric material conformally on the at least one opening, filling the at least one opening with a channel material.

### Claim 9

A method of fabricating a semiconductor structure, the method comprising:
forming at least one opening through a stack of alternating tier dielectric materials and tier control gate materials;
removing lateral portions of each of the tier control gate materials to form control gate recesses;
forming a charge blocking material on exposed surfaces of the tier dielectric materials and the tier control gate materials in the at least one opening, the charge blocking material comprising a charge trapping portion;
filling the control gate recesses with a charge storage material;
removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material; and
filling the air gaps with a conductive material,
wherein filling the air gaps comprises forming the conductive material in the air gaps.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the conductive material in the air gaps comprises forming a conductive material selected from the group consisting of undoped polysilicon, n-doped polysilicon, and p-doped polysilicon.

### Claim 11 (depends on 9)

A method of claim 9, wherein forming a charge blocking material on exposed surfaces of the tier dielectric materials and the tier control gate materials comprises forming the charge blocking material on recessed sidewalls of the tier control gate materials and on horizontal surfaces and vertical surfaces of the tier dielectric materials.

### Claim 12 (depends on 9)

The method of claim 9, further comprising conformally forming an undoped polysilicon material on exposed surfaces of the at least one opening.

### Claim 13 (depends on 12)

The method of claim 12, further comprising oxidizing the undoped polysilicon material to a tunnel oxide material.