# US 10,121,669 B2 · Flash memory fabrication method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,669 B2
- Document ID: US10121669B2
- Status: Granted
- Kind: B2
- Application number: 14/815,867
- Filed: 2015-07-31
- Published: 2016-03-03
- Granted: 2018-11-06
- Earliest claimed: 2014-08-28
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Jinhua Liu
- Web page: https://patentgrep.com/patent/US10121669B2

## CPC

- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/30: characterised by the memory core region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate comprising an active region, and successive layers of a tunnel oxide layer, a floating gate, a gate dielectric layer, a control gate overlying each other. A first portion of the tunnel oxide layer disposed on an edge of the active region has a thickness that is greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region. Such features ensure efficient reduction of read disturb errors of a Flash memory device.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate comprising an active region;
a tunnel oxide layer overlying the semiconductor substrate;
a shallow trench isolation structure disposed at opposite sides of the active region and having an upper surface flush with an upper surface of the semiconductor substrate;
a tunnel oxide thickness enhancing region disposed along a side surface of the shallow trench isolation structure adjacent to the active region and having an upper surface flush with an upper surface of the shallow trench isolation structure;
a floating gate overlying the tunnel oxide layer;
a gate dielectric layer overlying the floating gate; and
a control gate overlying the gate dielectric layer,
wherein a first portion of the tunnel oxide layer disposed on an edge of the active region and on the tunnel oxide thickness enhancing region has a thickness greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region, wherein the tunnel oxide thickness enhancing region is disposed below the first position of the tunnel oxide layer and spaced apart from the second portion of the tunnel oxide layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the thickness of the second portion of the tunnel oxide layer is about 89 Angstroms.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the tunnel oxide thickness enhancing region comprises F ions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) structure.

### Claim 5

A method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising an active region;
forming a hard mask on the semiconductor substrate;
etching the semiconductor substrate using the hard mask as a mask to form a trench;
performing an ion implantation onto the semiconductor layer to form a tunnel oxide thickness enhancing region along a side surface of the trench and adjacent to the active region;
forming a shallow trench isolation structure in the trench on the tunnel oxide thickness enhancing region;
removing the hard mask;
forming a tunnel oxide layer in a location previously occupied by the hard mask, wherein a first portion of the tunnel oxide layer disposed on the edge of the active region and on the tunnel oxide thickness enhancing region has a thickness greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region; and
forming a floating gate on the tunnel oxide layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the ion implantation comprises F ions.

### Claim 7 (depends on 5)

The method of claim 5, wherein forming the shallow trench isolation structure comprises:
filling an insulating material in the trench; and
performing a CMP process to remove excess of the insulating material over a surface of the hard mask.

### Claim 8 (depends on 5)

The method of claim 5, further comprising, after forming the floating gate:
removing excess of an insulating material filled in the shallow trench isolation structure that is over a surface of the semiconductor substrate;
forming a gate dielectric layer overlying the floating gate; and
forming a control gate overlying the gate dielectric layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the gate dielectric layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) structure.

### Claim 10 (depends on 5)

The method of claim 5, wherein the ion implantation comprises a fluorine gas (F2).

### Claim 11

An electronic device comprising an electronic component and a semiconductor device electrically connected with the electronic component, the semiconductor device comprising:
a semiconductor substrate comprising an active region;
a tunnel oxide layer overlying the semiconductor substrate;
a shallow trench isolation structure disposed at opposite sides of the active region and having an upper surface flush with an upper surface of the semiconductor substrate;
a tunnel oxide thickness enhancing region disposed along a side surface of the shallow trench isolation structure adjacent to the active region and having an upper surface flush with an upper surface of the shallow trench isolation structure;
a floating gate overlying the tunnel oxide layer;
a gate dielectric layer overlying the floating gate; and
a control gate overlying the gate dielectric layer,
wherein a first portion of the tunnel oxide layer disposed on an edge of the active region and on the tunnel oxide thickness enhancing region has a thickness greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region, wherein the tunnel oxide thickness enhancing region is disposed below the first position of the tunnel oxide layer and spaced apart from the second portion of the tunnel oxide layer.

### Claim 12 (depends on 11)

The electronic device of claim 11, wherein the tunnel oxide thickness enhancing region comprises F ions.

### Claim 13 (depends on 11)

The electronic device of claim 11, wherein the gate dielectric layer comprises a silicon oxide/silicon nitride/silicon oxide (ONO) structure.

### Claim 14 (depends on 11)

The electronic device of claim 11, wherein the semiconductor device comprises a flash memory device.

### Claim 15 (depends on 11)

The electronic device of claim 11, wherein the tunnel oxide thickness enhancing region has an elongated shape extending toward the semiconductor substrate in a direction perpendicular to the gate dielectric layer.