# US 10,121,668 B2 · Method of forming closed cell lateral MOSFET using silicide source

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- Number: US 10,121,668 B2
- Document ID: US10121668B2
- Status: Granted
- Kind: B2
- Application number: 15/814,829
- Filed: 2017-11-16
- Published: 2018-03-15
- Granted: 2018-11-06
- Earliest claimed: 2014-04-07
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Shekar Mallikarjunaswamy
- Web page: https://patentgrep.com/patent/US10121668B2

## CPC

- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/028: {of double-diffused metal oxide semiconductor [DMOS] FETs}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.

## Claims

### Claim 1

A method for forming a closed cell lateral MOS transistor, comprising:
providing a semiconductor layer of a first conductivity type forming the body of the transistor and being lightly doped;
forming a conductive gate overlying and insulated from a top surface of the semiconductor layer by a gate dielectric layer, the conductive gate forming a mesh having a plurality of openings, the plurality of openings defining a cellular array of source cells and drain cells;
forming sidewall spacers on sidewalls of the conductive gate;
forming a plurality of diffusion regions of a second conductivity type, opposite the first conductivity type, in the semiconductor layer exposed by the openings in the mesh, the plurality of diffusion regions forming the cellular array of source cells and drain cells, wherein alternating rows of the diffusion regions form source regions and drain regions of the transistor, and the semiconductor layer under the conductive gate between the source regions and the drain regions forms the channel of the transistor;
forming a body diffusion region of the first conductivity type in each of source cells in the cellular array of source and drain cells, the body diffusion region being more heavily doped than the semiconductor layer and being encircled by the source region in each of the source cell, wherein the body diffusion region is formed centered in the source cell surrounded by the source region;
forming a metal silicide layer on a top surface of the plurality of diffusion regions and the body diffusion regions, the metal silicide layer being formed in the source cells to electrically connect the source region and the body diffusion region formed in each of the source cells; and
forming a source/body contact in each of the source cells and in contact with the metal silicide layer, the source/body contact being electrically connected to the source region and the body diffusion region in each of the source cells through the metal silicide layer, wherein the source/body contact is positioned above the body diffusion region only in the source cell and the source/body contact has a dimension smaller than a dimension of the body diffusion region in the source cell at the top surface of the semiconductor layer, and wherein the sidewall spacer is positioned between the conductive gate and the metal silicide layer, and the source/body contact is separated from the sidewall spacer by a dielectric material,
wherein the source/body contact in each of the source cells comprises a contact having minimally sized dimension and minimal spacing to the conductive gate surrounding the respective source cell.

### Claim 2 (depends on 1)

The method of claim 1, wherein providing the semiconductor layer of the first conductivity type comprises:
providing a well of the first conductivity type formed on a semiconductor substrate, the well forming the body of the transistor.

### Claim 3 (depends on 1)

The method of claim 1, wherein providing the semiconductor layer of the first conductivity type comprises:
providing a well of the first conductivity type formed in an epitaxial layer formed on a semiconductor substrate, the well forming the body of the transistor.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the body diffusion region of the first conductivity type in each of source cells comprises:
forming the body diffusion region and the source region as overlapping diffusion regions.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the conductive gate including forming the mesh having a plurality of openings comprises:
forms a mesh having a plurality of substantially identically sized openings.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the conductive gate including forming the mesh having a plurality of openings comprises:
forms a mesh having a first plurality of openings having a first periphery length for forming the source cells and a second plurality of openings having a second periphery length for forming the drain cells, the first periphery length being greater than the second periphery length.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming a source/body contact comprises forming a tungsten plug contact.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.

### Claim 9

A method for forming a closed cell lateral MOS transistor, comprising:
providing a semiconductor layer of a first conductivity type forming the body of the transistor, the semiconductor layer being lightly doped;
forming a conductive gate overlying and insulated from a top surface of the semiconductor layer by a gate dielectric layer, the conductive gate forming a mesh having a plurality of openings, the plurality of openings defining a cellular array of source cells and drain cells;
forming sidewall spacers on sidewalls of the conductive gate;
forming a plurality of diffusion regions of a second conductivity type, opposite the first conductivity type, in the semiconductor layer exposed by the openings in the mesh, the plurality of diffusion regions forming the cellular array of source cells and drain cells, wherein alternating rows of the diffusion regions form source regions and drain regions of the transistor, and the semiconductor layer under the conductive gate between the source regions and the drain regions forms the channel of the transistor;
forming a body diffusion region of the first conductivity type in each of the source cells in the cellular array of source and drain cells, the body diffusion region being more heavily doped than the semiconductor layer and being encircled by the source region in each of the source cell;
forming a metal silicide layer on a top surface of the plurality of diffusion regions and the body diffusion regions, the metal silicide layer being formed in the source cells to electrically connect the source region and the body diffusion region formed in each of the source cells;
forming a dielectric layer formed over the semiconductor layer, the conductive gate and the sidewall spacers, the dielectric layer including a plurality of contact openings exposing at least the source cells, each contact opening being formed in a respective source cell to expose at least a portion of the source region and at least a portion of the body region formed in the respective source cell, and at least one sidewall of the contact opening overlapping the sidewall spacer formed on at least one sidewall of the conductive gate to expose a lower portion of the sidewall spacer; and
forming a source/body contact in the contact opening of each of the source cells and in contact with the metal silicide layer, the source/body contact being electrically connected to the source region and the body diffusion region in each of the source cells through the metal silicide layer, the source/body contact being isolated from the conductive gate by the sidewall spacers.

### Claim 10 (depends on 9)

The method of claim 9, wherein providing the semiconductor layer of the first conductivity type comprises:
providing a well of the first conductivity type formed on a semiconductor substrate, the well forming the body of the transistor.

### Claim 11 (depends on 9)

The method of of claim 9, wherein providing the semiconductor layer of the first conductivity type comprises:
providing a well of the first conductivity type formed in an epitaxial layer formed on a semiconductor substrate, the well forming the body of the transistor.

### Claim 12 (depends on 9)

The method of claim 9, wherein forming a body diffusion region of the first conductivity type in each of the source cells comprises:
forming the body region centered in the source cell surrounded by the source region.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the body diffusion region of the first conductivity type in each of the source cells comprises:
forming the body diffusion region and the source region as overlapping diffusion regions.

### Claim 14 (depends on 9)

The method of claim 9, wherein forming the conductive gate including forming the mesh having a plurality of openings comprises:
forms the mesh having a plurality of substantially identically sized openings.

### Claim 15 (depends on 9)

The method of claim 9, wherein forming a source/body contact in the contact opening of each of the source cells comprises:
forming a stripe contact having an elongated shape, wherein two narrow ends of the stripe contact overlap the sidewall spacers formed on the sidewalls of the conductive gate surrounding the respective source cell to expose the lower portion of the sidewall spacers.

### Claim 16 (depends on 9)

The method of claim 9, wherein forming a source/body contact in the contact opening of each of the source cells comprises:
forming a contact having a cross shape, wherein at least four ends of the cross-shaped contact opening overlap the sidewall spacers formed on the sidewalls of the conductive gate surrounding the respective source cell to expose the lower portion of the sidewall spacers.

### Claim 17 (depends on 9)

The method of claim 9, wherein forming a source/body contact comprises forming a tungsten plug contact.

### Claim 18 (depends on 9)

The method of claim 9, wherein the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.