# US 10,121,642 B2 · Digital electron amplifier with anode readout devices and methods of fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,642 B2 - Document ID: US10121642B2 - Status: Granted - Kind: B2 - Application number: 15/952,973 - Filed: 2018-04-13 - Published: 2018-08-16 - Granted: 2018-11-06 - Earliest claimed: 2015-04-23 - Assignees: Uchicago Argonne, LLC - Applicants: UChicago Argonne, LLC - Inventors: Anil U. Mane; Jeffrey W. Elam - Web page: https://patentgrep.com/patent/US10121642B2 ## CPC - H01J 43/246: {Microchannel plates [MCP] (image amplification tubes using MCP H01J31/507)} - H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H) ## Abstract Scalable electron amplifier devices and methods of fabricating the devices an atomic layer deposition (“ALD”) fabrication process are described. The ALD fabrication process allows for large area (e.g., eight inches by eight inches) electron amplifier devices to be produced at reduced costs compared to current fabrication processes. The ALD fabrication process allows for nanostructure functional coatings, to impart a desired electrical conductivity and electron emissivity onto low cost borosilicate glass micro-capillary arrays to form the electron amplifier devices. ## Claims ### Claim 1 A method of fabricating a digital electron amplifier system on chip, the method comprising: providing a base substrate having a top surface; depositing an insulating layer on the top surface of the base substrate; providing an anode structure on top of the insulating layer; depositing an insulating oxide layer on top of the anode structure; forming an electron amplification structure (“EAS”) on top of the insulating oxide layer, the EAS having a bottom electrical contact, a top electrical contact, and a resistive layer positioned in between the bottom electrical contact and the top electrical contact; and forming electron amplification pores, each of the electron amplification pores passing through the top electrical contact, the resistive layer, the bottom electrical contact, and the insulating oxide layer thereby exposing the anode structure at a bottom of each of the electron amplification pores and each of the electron amplification pores defined by an electron amplification pore wall; and depositing a secondary electron emission (“SEE”) layer on the each of the electron amplification pore walls, the SEE layer selected from a material configured to emit secondary electrons when a primary electron impacts the SEE layer while a bias voltage is applied across the SEE layer. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the electron amplification pores includes orienting the digital electron amplifier system on chip at a non-perpendicular bias angle with respect to an etching device that forms the pores to cause the electron amplification pores to be oriented with the bias angle such that the electron amplification pores are not perpendicular with respect to the top surface of the base substrate. ### Claim 3 (depends on 1) The method of claim 1, wherein the SEE is a uniform layer on the electron amplification pores walls. ### Claim 4 (depends on 3) The method of claim 3, wherein depositing the SEE layer covers a bottom of each of the electron amplification pores thereby covering the anode structure with the SEE layer, and wherein the method further comprises removing a portion of the SEE layer that covers the anode structure from each of the electron amplification pores. ### Claim 5 (depends on 1) The method of claim 1, further comprising cleaning the base substrate through a wet cleaning process or a dry cleaning process. ### Claim 6 (depends on 1) The method of claim 1, wherein the base substrate is a flexible substrate. ### Claim 7 (depends on 1) The method of claim 1, wherein the anode structure is shaped into a serpentine pattern using electron beam writing, photolithography, or an etching process. ### Claim 8 (depends on 1) The method of claim 1, wherein: the EAS is a first EAS; the electron amplification pores are first electron amplification pores; and the method further comprises: forming a second EAS structure on top of the first EAS structure, the second EAS structure having a second resistive layer and a second top electrical contact, the second resistive layer positioned between the top electrical contact of the first EAS and the second top electrical contact of the second EAS; and forming second electron amplification pores, each of the second electron amplification pores passing through the second top electrical contact and the second resistive layer, the second amplification pores line up with and connect to the first electron amplification pores of the first EAS. ### Claim 9 (depends on 8) The method of claim 8 wherein the second electron amplification pores have a different bias angle than the first electron amplification pores with respect to the base substrate. ### Claim 10 (depends on 1) The method of claim 1, wherein the digital electron amplifier system on chip is at least eight inches by eight inches in size. ### Claim 11 A method of fabricating a secondary electron emission layer within electron amplification pores, the method comprising: forming an electron amplification structure (“EAS”) on top of an insulating oxide layer of an anode structure, the EAS having a bottom electrical contact, a top electrical contact, and a resistive layer positioned in between the bottom electrical contact and the top electrical contact; and forming electron amplification pores, each of the electron amplification pores passing through the top electrical contact, the resistive layer, the bottom electrical contact, and the insulating oxide layer thereby exposing the anode structure at a bottom of each of the electron amplification pores and each of the electron amplification pores defined by an electron amplification pore wall; depositing a secondary electron emission (“SEE”) layer uniformly on the each of the electron amplification pore walls, the SEE layer selected from a material configured to emit secondary electrons when a primary electron impacts the SEE layer while a bias voltage is applied across the SEE layer. ### Claim 12 (depends on 11) The method of claim 11, wherein depositing the SEE layer covers a bottom of each of the electron amplification pores thereby covering the anode structure with the SEE layer, and wherein the method further comprises removing a portion of the SEE layer that covers the anode structure from each of the electron amplification pores. ### Claim 13 (depends on 11) The method of claim 11, wherein: the EAS is a first EAS; the electron amplification pores are first electron amplification pores; and the method further comprises: forming a second EAS structure on top of the first EAS structure, the second EAS structure having a second resistive layer and a second top electrical contact, the second resistive layer positioned between the top electrical contact of the first EAS and the second top electrical contact of the second EAS; and forming second electron amplification pores, each of the second electron amplification pores passing through the second top electrical contact and the second resistive layer, the second amplification pores line up with and connect to the first electron amplification pores of the first EAS. ### Claim 14 (depends on 13) The method of claim 13, wherein the second electron amplification pores have a different bias angle than the first electron amplification pores.