# US 10,121,556 B2 · Designing method of semiconductor device and semiconductor device

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- Number: US 10,121,556 B2
- Document ID: US10121556B2
- Status: Granted
- Kind: B2
- Application number: 14/968,116
- Filed: 2015-12-14
- Published: 2016-08-04
- Granted: 2018-11-06
- Earliest claimed: 2015-01-29
- Assignees: Socionext Inc.
- Applicants: Socionext Inc.
- Inventors: Tetsuo Ashizawa
- Web page: https://patentgrep.com/patent/US10121556B2

## CPC

- G11C 29/36: Data generation devices, e.g. data inverters
- G11C 29/38: Response verification devices
- G11C 2029/3602: {Pattern generator}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory circuit with a built-in memory BIST circuit is created by: arranging a block of a clock pulse generator and a plurality of blocks of input/output circuits each corresponding to each of inputted/outputted bits adjacently in a first direction; arranging a block of a BIST pattern generator of the memory BIST circuit which is laid out so that signal wiring is connected by being arranged adjacently and performs generation of a test pattern, adjacently to the block of the clock pulse generator in a second direction; and arranging a plurality of blocks of comparators of the memory BIST circuit which are laid out so that signal wirings are connected by being arranged adjacently and compare an output value and an expected value, adjacently to the plurality of blocks of the input/output circuits in the second direction with the same pitch as that of the input/output circuits.

## Claims

### Claim 1

A semiconductor device comprising a memory circuit with a memory built-in self test circuit therein,
the memory circuit including:
a pulse generator;
a plurality of input and output circuits configured to input and output data and being arranged adjacently to the pulse generator in a first direction and each of the plurality of input and output circuits being corresponding to each of bits of the data to be inputted and outputted;
a pattern generator of the memory built-in self test circuit configured to perform generation of a test pattern and being arranged adjacently to the pulse generator in a second direction different from the first direction, between the pattern generator and the pulse generator wiring of a signal to be transmitted being connected by being arranged adjacently to the pulse generator; and
a same number of a plurality of comparators of the memory built-in self test circuit as a number of the plurality of input and output circuits, each of the plurality of comparators being configured to compare an output value to be supplied from each of the input and output circuits respectively and an expected value to be supplied from the pattern generator, the plurality of comparators being arranged adjacently to the plurality of input and output circuits in the second direction with a same pitch as a pitch of the plurality of input and output circuits, between the plurality of comparators and the plurality of input and output circuits wirings of signals to be transmitted being connected by being arranged adjacently to the plurality of input and output circuits.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the pattern generator includes an address counter configured to generate an address to be used for a test and a check circuit configured to limit the address generated by the address counter in accordance with the memory circuit.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the pattern generator includes a power switch configured to supply power to the memory built-in self test circuit at a time of a test and to cut off supply of the power to the memory built-in self test circuit except at the time of the test.