# US 10,121,555 B2 · Wear-limiting non-volatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,555 B2 - Document ID: US10121555B2 - Status: Granted - Kind: B2 - Application number: 15/267,092 - Filed: 2016-09-15 - Published: 2017-11-30 - Granted: 2018-11-06 - Earliest claimed: 2016-05-26 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Amro Awad; Sergey Blagodurov - Web page: https://patentgrep.com/patent/US10121555B2 ## CPC - G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically} - G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]} - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. The non-volatile memory controller includes a flash translation layer to correlate read and write requests for data having a logical address between the reading and writing the data to physical address location of the non-volatile flash memory. The flash translation layer, when writing to a physical address location, chooses between a wear-leveling circuit and a wear-limiting circuit to select the physical address location. ## Claims ### Claim 1 A memory device, comprising: at least one non-volatile memory configured to read and write data; and a controller including a first circuit and a second circuit, the controller being configured to: receive a write request, select one of the first circuit and the second circuit and initiate the selected one of the first circuit and the second circuit to complete the request, wherein, when the first circuit is initiated, the first circuit is configured to determine a physical address for a least used page in the non-volatile memory and cause data associated with the write request to be written to the least used page, and wherein, when the second circuit is initiated, the second circuit is configured to determine a physical address for a page in the non-volatile memory where the data associated with the write request was last stored, identify cells of the data that have changed, and cause only those cells of the data that have changed to be written to the page where the data was last stored, wherein any data that is stored in the non-volatile memory is organized into pages, each page including a plurality of cells, wherein the first circuit includes a wear-leveling circuit and the second circuit includes a wear-limiting circuit. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the controller is further configured to: identify a value of a flag associated with the write request; select the first circuit to complete the write request when the flag has a first value; and select the second circuit to complete the write request when the flag has a second value. ### Claim 3 (depends on 1) The memory device of claim 1, where the first circuit and the second circuit are part of a flash translation layer that is operable to translate a logical address associated with the write request to a corresponding physical address of a location in the non-volatile memory. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the non-volatile memory includes a flash memory. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the second circuit is further configured to: detect a count of swaps performed on the page where the data was last stored; complete the write request when the count of swaps is less than a threshold; and forward the write request to the first circuit when the count of swaps is greater than the threshold. ### Claim 6 (depends on 1) The memory device of claim 1, wherein: the controller includes a flag check circuit for detecting a value of a flag; and the selection of one of the first circuit and the second circuit is performed based on the value of the flag. ### Claim 7 A method for storing data in a non-volatile memory device, the non-volatile memory device including a non-volatile memory and a controller, the controller including a first circuit and a second circuit, the method comprising: receiving, by the controller, a write request, selecting, by the controller, one of the first circuit and the second circuit and completing the write request using the selected one of the first circuit and the second circuit, wherein completing the write request with the first circuit includes determining a physical address for a least used page in the non-volatile memory, and causing data associated the write request to be written to the least used page, and wherein completing the write request with the second circuit includes determining a physical address for a page in the non-volatile memory where the data associated with the write request was last stored, identifying cells of the data that have changed, and causing only those cells of the data that have changed to be written to the page where the data was last stored, wherein any data that is stored in the non-volatile memory is organized into pages, each page including a plurality of cells, wherein the first circuit includes a wear-leveling circuit and the second circuit includes a wear-limiting circuit. ### Claim 8 (depends on 7) The method of claim 7, further comprising identifying a value of a flag associated with the write request, wherein: the first circuit is selected to complete the write request when the flag has a first value; and the second circuit is selected to complete the write request when the flag has a second value. ### Claim 9 (depends on 7) The method of claim 7, wherein the second circuit and the first circuit are part of a flash translation layer that is operable to translate a logical address associated with the write request to a corresponding physical address of a location in the non-volatile memory. ### Claim 10 (depends on 7) The method of claim 7, wherein the non-volatile memory includes a flash memory. ### Claim 11 (depends on 7) The method of claim 7, further comprising, detecting a count of swaps performed on the page where the data was last stored, wherein the write request is completed by the second circuit only when the count of swaps is less than a threshold. ### Claim 12 A non-transitory computer-readable medium having instructions stored thereon, which when executed by at least one controller cause the at least one controller to perform a method, comprising: receiving a write request, selecting one of a second circuit and a first circuit and completing the write request using the selected one of the first circuit and the second circuit, wherein completing the write request with the first circuit includes determining a physical address for at least used page in a non-volatile memory, and causing data associated the write request to be written to the least used page, and wherein completing the write request with the second circuit includes determining a physical address for a page in the non-volatile memory where the data associated with the write request was last stored, identifying cells of the data that have changed, and causing only those cells of the data that have changed to be written to the page where the data was last stored, wherein any data that is stored in the non-volatile memory is organized into pages, each page including a plurality of cells, wherein the first circuit includes a wear-leveling circuit and the second circuit includes a wear-limiting circuit. ### Claim 13 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the method further comprises identifying a value of a flag associated with the write request, wherein: the first circuit is selected to complete the write request when the flag has a first value; and the second circuit is selected to complete the write request when the flag has a second value. ### Claim 14 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the non-volatile memory includes a flash memory. ### Claim 15 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the method further comprises detecting a count of swaps performed on the page where the data was last stored, wherein the write request is completed by the second circuit only when the count of swaps is less than a threshold.