# US 10,121,550 B2 · Power switch circuit

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- Number: US 10,121,550 B2
- Document ID: US10121550B2
- Status: Granted
- Kind: B2
- Application number: 15/397,043
- Filed: 2017-01-03
- Published: 2017-07-20
- Granted: 2018-11-06
- Earliest claimed: 2016-01-19
- Assignees: eMemory Technology Inc.
- Applicants: eMemory Technology Inc.
- Inventors: Chih-Yang Huang; Wei-Ming Ku
- Web page: https://patentgrep.com/patent/US10121550B2

## CPC

- G11C 16/30: Power supply circuits
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 8/10: Decoders
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 16/0458: {comprising two or more independent floating gates which store independent data}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B 41/10: characterised by the top-view layout
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 89/10: Integrated device layouts
- H10W 20/43: Layouts of interconnections
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first transistor receive a first supply voltage and a second supply voltage, respectively. A second source/drain terminal and a body terminal of the first transistor are connected with a node z. An output signal is outputted from the node z. A first source/drain terminal and a gate terminal of the second transistor receive the second supply voltage and the first supply voltage, respectively. A second source/drain terminal and a body terminal of the second transistor are connected with the node z. The current source is connected between a bias voltage and the node z. The first supply voltage, the second supply voltage or the bias voltage is selected as the output signal.

## Claims

### Claim 1

A power switch circuit, comprising:
a first transistor, wherein a first source/drain terminal of the first transistor receives a first supply voltage, a second source/drain terminal of the first transistor is connected with a node z, a gate terminal of the first transistor receives a second supply voltage, a body terminal of the first transistor is connected with the node z, and an output signal is outputted from the node z;
a second transistor, wherein a first source/drain terminal of the second transistor receives the second supply voltage, a second source/drain terminal of the second transistor is connected with the node z, a gate terminal of the second transistor receives the first supply voltage, and a body terminal of the second transistor is connected with the node z;
a third transistor, wherein a first source/drain terminal of the third transistor receives a bias voltage, a second source/drain terminal of the third transistor is connected with the node z, a gate terminal of the third transistor receives a shifted signal, and a body terminal of the third transistor is connected with the node z;
an automatic selection circuit receiving the first supply voltage and the second supply voltage and generating an output voltage, wherein if the first supply voltage is lower than the second supply voltage, the first supply voltage is selected as the output voltage, wherein if the first supply voltage is higher than the second supply voltage, the second supply voltage is selected as the output voltage; and
a level shifter for converting a control signal into the shifted signal according to the control signal and the output voltage of the automatic selection circuit.

### Claim 2 (depends on 1)

The power switch circuit as claimed in claim 1, wherein the bias voltage is equal to the first supply voltage, or the bias voltage is equal to the second supply voltage.

### Claim 3 (depends on 1)

The power switch circuit as claimed in claim 1, wherein the first transistor, the second transistor and the third transistor are n-type transistors.

### Claim 4 (depends on 1)

The power switch circuit as claimed in claim 1, wherein the automatic selection circuit comprises:
a fourth transistor, wherein a first source/drain terminal of the fourth transistor receives the first supply voltage, a second source/drain terminal of the fourth transistor generates the output voltage, a gate terminal of the fourth transistor receives the second supply voltage, and a body terminal of the fourth transistor is connected with the second source/drain terminal of the fourth transistor; and
a fifth transistor, wherein a first source/drain terminal of the fifth transistor receives the second supply voltage, a second source/drain terminal and a body terminal of the fifth transistor are connected with the second source/drain terminal of the fourth transistor, and a gate terminal of the fifth transistor receives the first supply voltage.

### Claim 5 (depends on 1)

The power switch circuit as claimed in claim 1, further comprising:
a fourth transistor, wherein a first source/drain terminal and a body terminal of the fourth transistor receive the first supply voltage, a second source/drain terminal of the fourth transistor is connected with a node a, and a gate terminal of the fourth transistor receives the second supply voltage;
a fifth transistor, wherein a first source/drain terminal and a body terminal of the fifth transistor receive the second supply voltage, a second source/drain terminal of the fifth transistor is connected with a node b, and a gate terminal of the fifth transistor receives the first supply voltage;
a first current source connected between a voltage source and the node a;
a second current source connected between the voltage source and the node b; and
an AND gate, wherein two input terminals of the AND gate are respectively connected with the node a and the node b, and an output terminal of the AND gate generates the control signal.

### Claim 6

A power switch circuit, comprising:
a first transistor, wherein a first source/drain terminal of the first transistor receives a first supply voltage, a second source/drain terminal of the first transistor is connected with a node w, a gate terminal of the first transistor receives a first shifted signal, and an output signal is outputted from the node w;
a second transistor, wherein a first source/drain terminal of the second transistor receives the second supply voltage, a second source/drain terminal of the second transistor is connected with the node w, and a gate terminal of the second transistor receives a second shifted signal;
a first automatic selection circuit receiving the first supply voltage and the second supply voltage and generating an output voltage, wherein if the first supply voltage is lower than the second supply voltage, the first supply voltage is selected as the output voltage, wherein if the first supply voltage is higher than the second supply voltage, the second supply voltage is selected as the output voltage;
a first level shifter for converting a first control signal into the first shifted signal according to the first control signal and the output voltage of the first automatic selection circuit; and
a second level shifter for converting a second control signal into the second shifted signal according to the second control signal and the output voltage of the first automatic selection circuit.

### Claim 7 (depends on 6)

The power switch circuit as claimed in claim 6, wherein the first transistor and the second transistor are n-type transistors.

### Claim 8 (depends on 6)

The power switch circuit as claimed in claim 6, wherein the first automatic selection circuit comprises:
a third transistor, wherein a first source/drain terminal of the third transistor receives the first supply voltage, a second source/drain terminal of the third transistor generates the output voltage, a gate terminal of the third transistor receives the second supply voltage, and a body terminal of the third transistor is connected with the second source/drain terminal of the third transistor; and
a fourth transistor, wherein a first source/drain terminal of the fourth transistor receives the second supply voltage, a second source/drain terminal and a body terminal of the fourth transistor are connected with the second source/drain terminal of the third transistor, and a gate terminal of the fourth transistor receives the first supply voltage.

### Claim 9 (depends on 6)

The power switch circuit as claimed in claim 6, further comprising:
a second automatic selection circuit receiving the first supply voltage and the output signal and generating a first body voltage to a body terminal of the first transistor, wherein if the first supply voltage is lower than the output signal, the first supply voltage is selected as the first body voltage, wherein if the first supply voltage is higher than the output signal, the output signal is selected as the first body voltage; and
a third automatic selection circuit receiving the second supply voltage and the output signal and generating a second body voltage to a body terminal of the second transistor, wherein if the second supply voltage is lower than the output signal, the second supply voltage is selected as the second body voltage, wherein if the second supply voltage is higher than the output signal, the output signal is selected as the second body voltage.

### Claim 10 (depends on 6)

The power switch circuit as claimed in claim 6, further comprising:
a third transistor, wherein a first source/drain terminal of the third transistor receives a bias voltage, a second source/drain terminal of the third transistor is connected with the node w, and a gate terminal of the third transistor receives a third shifted signal; and
a third level shifter for converting a third control signal into the third shifted signal according to the third control signal and the output voltage,
wherein when the first control signal and the second control signal are in a first logic level state, the third control signal is in a second logic level state.

### Claim 11 (depends on 10)

The power switch circuit as claimed in claim 10, wherein the bias voltage is equal to the first supply voltage, or the bias voltage is equal to the second supply voltage.

### Claim 12 (depends on 10)

The power switch circuit as claimed in claim 10, further comprising:
a fourth transistor, wherein a first source/drain terminal and a body terminal of the fourth transistor receive the first supply voltage, a second source/drain terminal of the fourth transistor is connected with a node c, and a gate terminal of the fourth transistor receives the second supply voltage;
a fifth transistor, wherein a first source/drain terminal and a body terminal of the fifth transistor receive the second supply voltage, a second source/drain terminal of the fifth transistor is connected with a node d, and a gate terminal of the fifth transistor receives the first supply voltage;
a first current source connected between a voltage source and the node c;
a second current source connected between the voltage source and the node d; and
an AND gate, wherein two input terminals of the AND gate are respectively connected with the node c and the node d, and an output terminal of the AND gate generates the third control signal.

### Claim 13 (depends on 6)

The power switch circuit as claimed in claim 6, further comprising a weak current source, wherein the weak current source is connected between a bias voltage and the node w.

### Claim 14 (depends on 13)

The power switch circuit as claimed in claim 13, wherein the bias voltage is equal to the first supply voltage, or the bias voltage is equal to the second supply voltage.