# US 10,121,545 B2 · Semiconductor memory device and operating method for inhibiting programming

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- Number: US 10,121,545 B2
- Document ID: US10121545B2
- Status: Granted
- Kind: B2
- Application number: 15/130,593
- Filed: 2016-04-15
- Published: 2017-05-25
- Granted: 2018-11-06
- Earliest claimed: 2015-11-23
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hae Soon Oh
- Web page: https://patentgrep.com/patent/US10121545B2

## CPC

- G11C 16/12: Programming voltage switching circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising: setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode; setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode; performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode, upon success of the program verification operation to the i-th program status.

## Claims

### Claim 1

An operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising:
setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode;
setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode;
performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and
immediately changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode when the program verification operation to the i-th program status succeeds,
wherein the k is an integer greater than or equal to 2.

### Claim 2 (depends on 1)

The operating method of claim 1, wherein the performing of the program operation includes:
providing a program permit voltage to the first group of the memory cells; and
providing a program inhibit voltage to the second group of the memory cells.

### Claim 3 (depends on 1)

The operating method of claim 1, wherein the changing comprises:
determining the success of the program verification operation to the i-th program status when threshold voltages of the memory cells having the i-th program status reaches the i-th program status.

### Claim 4

A semiconductor memory device, comprising:
a plurality of memory cells each having one of “n” number of program statuses as a target program status; and
a peripheral circuit configured to:
set a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode;
set a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode;
perform a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and
immediately change one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode when the program verification operation to the i-th program status succeeds,
wherein the k is an integer greater than or equal to 2.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein the peripheral circuit provides a program permit voltage to the first group of the memory cells, and provides a program inhibit voltage to the second group of the memory cells during the program operation.

### Claim 6 (depends on 4)

The semiconductor memory device of claim 4, wherein the peripheral circuit determines the success of the program verification operation to the i-th program status when threshold voltages of the memory cells having the i-th program status reaches the i-th program status during the changing.