# US 10,121,544 B2 · Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,544 B2 - Document ID: US10121544B2 - Status: Granted - Kind: B2 - Application number: 15/692,565 - Filed: 2017-08-31 - Published: 2017-12-28 - Granted: 2018-11-06 - Earliest claimed: 2016-06-24 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Qiang Tang; Ramin Ghodsi; Toru Tanzawa - Web page: https://patentgrep.com/patent/US10121544B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 16/12: Programming voltage switching circuits - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time. ## Claims ### Claim 1 A programming method, comprising: applying a voltage to a selected access line commonly connected to control gates of a plurality of memory cells, wherein each memory cell of the plurality of memory cells is contained in a respective string of series-connected memory cells of a plurality of strings of series-connected memory cells; and while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time; wherein the subset of the plurality of memory cells comprises more than one memory cell. ### Claim 2 (depends on 1) The method of claim 1, wherein each memory cell of the subset of the plurality of memory cells is contained in a respective string of series-connected memory cells of a subset of the plurality of strings of series-connected memory cells, wherein electrically connecting the subset of the plurality of memory cells to the one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time comprises respectively activating respective select transistors of a plurality of select transistors one at a time, wherein the respective select transistors of the plurality of select transistors are commonly connected to the data line and are respectively connected to the respective strings of series-connected memory cells of the subset of the plurality of strings of series-connected memory cells. ### Claim 3 (depends on 1) The method of claim 1, wherein a number of memory cells in the subset of the plurality of memory cells is equal to a number of page buffers connected to the one data line. ### Claim 4 (depends on 3) The method of claim 3, wherein each of the page buffers connected to the one data line stores data to be programmed in a respective memory cell of the subset of the plurality of memory cells. ### Claim 5 (depends on 1) The method of claim 1, wherein a respective single bit of data is to be programmed to each memory cell in the subset of the plurality of memory cells when the memory cells in the subset of the plurality of memory cells operate in a single-bit-per-memory-cell mode and wherein a number of bits equal to a number of the memory cells in the subset of the plurality of memory cells is to be programmed to one of the memory cells of the plurality of memory cells when the memory cells of the plurality of memory cells operate in a multiple-bit-per-memory-cell mode. ### Claim 6 (depends on 1) The method of claim 1, wherein electrically connecting the subset of the plurality of memory cells to the one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time while the voltage applied to the selected access line remains at the program voltage without being discharged programs data in each of the memory cells of the subset of the plurality of memory cells, and further comprising: reading the data programmed in each of the memory cells of the subset of the plurality of memory cells from each of the memory cells of the subset of the plurality of memory cells; and programming the data read from each of the memory cells of the subset of the plurality of memory cells to a single memory cell connected to an access line different than the selected access line. ### Claim 7 (depends on 6) The method of claim 6, wherein the data programmed in each of the memory cells of the subset of the plurality of memory cells comprises a plurality of bits of data. ### Claim 8 A programming method, comprising: applying a program voltage to a selected access line commonly connected to control gates of a plurality of memory cells, wherein each memory cell of the plurality of memory cells is contained in a respective string of series-connected memory cells of a plurality of strings of series-connected memory cells; and while the voltage applied to the selected access line remains at the program voltage without being discharged, sequentially electrically connecting a subset of the plurality of memory cells to one data line, each for a respective period of time, so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time. ### Claim 9 (depends on 8) The method of claim 8, further comprising: electrically isolating all memory cells of the subset of the plurality of memory cells from the one data line between the respective periods of time. ### Claim 10 (depends on 8) The method of claim 8, further comprising programming respective data into each of the memory cells of the subset of the plurality of memory cells during its respective period of time. ### Claim 11 (depends on 10) The method of claim 10, further comprising: reading the respective data programmed in each of the memory cells of the subset of the plurality of memory cells; and programming the data read from each of the memory cells of the subset of the plurality of memory cells to a single memory cell connected to an access line different than the selected access line. ### Claim 12 (depends on 11) The method of claim 11, wherein programming the data read from each of the memory cells of the subset of the plurality of memory cells to the single memory cell comprises programming a plurality of bits of data to the single memory cell. ### Claim 13 (depends on 8) The method of claim 8, wherein sequentially electrically connecting the subset of the plurality of memory cells to the one data line during their respective periods of time comprises, for each of the memory cells of the subset of the plurality of memory cells, activating a respective select gate between that memory cell of the subset of the plurality of memory cells and the one data line during its respective period of time. ### Claim 14 (depends on 13) The method of claim 13, further comprising electrically isolating all memory cells of the subset of the plurality of memory cells from the one data line between activating the respective select gate of one memory cell of the subset of the plurality of memory cells and activating the respective select gate of a next memory cell of the subset of the plurality of memory cells in sequence. ### Claim 15 (depends on 14) The method of claim 14, wherein electrically isolating all memory cells of the subset of the plurality of memory cells from the one data line comprises deactivating the respective select gates for all memory cells of the subset of the plurality of memory cells. ### Claim 16 (depends on 8) The method of claim 8, further comprising: while applying the program voltage to the selected access line and while sequentially electrically connecting the subset of the plurality of memory cells to the one data line, activating each memory cell of the plurality of strings of series-connected memory cells that does not have a control gate connected to the selected access line. ### Claim 17 A programming method, comprising: applying a program voltage to a selected access line commonly connected to control gates of a plurality of memory cells, wherein each memory cell of the plurality of memory cells is contained in a respective string of series-connected memory cells of a plurality of strings of series-connected memory cells; and while the voltage applied to the selected access line remains at the program voltage without being discharged, sequentially electrically connecting a subset of the plurality of memory cells to one data line, each for a respective period of time, so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time; wherein sequentially electrically connecting the subset of the plurality of memory cells to the one data line comprises: electrically connecting one memory cell of the subset of the plurality of memory cells to the one data line during its respective period of time while electrically isolating each remaining memory cell of the subset of the plurality of memory cells from the one data line; and electrically isolating that one memory cell of the subset of the plurality of memory cells from the one data line after its respective period of time and before electrically connecting any other memory cell of the subset of the plurality of memory cells to the one data line for its respective period of time. ### Claim 18 (depends on 17) The method of claim 17, further comprising, for each memory cell of the subset of the plurality of memory cells, while electrically connecting that memory cell to the one data line during its respective period of time, applying a respective voltage level to the one data line corresponding to a respective desired data value to be programmed to that memory cell. ### Claim 19 (depends on 18) The method of claim 18, wherein the respective voltage level corresponding to a particular desired data value inhibits changing a threshold voltage of its respective memory cell while applying the program voltage, and wherein the respective voltage level corresponding to a different desired data value enables changing the threshold voltage of its respective memory cell while applying the program voltage. ### Claim 20 (depends on 18) The method of claim 18, further comprising, for each memory cell of the subset of the plurality of memory cells, storing an indication of the respective desired data value for that memory cell in a respective page buffer of a plurality of page buffers connected to the one data line.