# US 10,121,540 B1 · Selector device for two-terminal memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,540 B1 - Document ID: US10121540B1 - Status: Granted - Kind: B1 - Application number: 15/797,447 - Filed: 2017-10-30 - Granted: 2018-11-06 - Earliest claimed: 2014-03-11 - Assignees: Crossbar, Inc. - Applicants: Crossbar, Inc. - Inventors: Sung Hyun Jo - Web page: https://patentgrep.com/patent/US10121540B1 ## CPC - G11C 13/0097: {Erasing, e.g. resetting, circuits or methods} - G11C 11/1659: {Cell access} - G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]} - G11C 13/003: {Cell access} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0061: {Timing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10B 63/22: {of the metal-insulator-metal type} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10B 63/845: {the switching components being connected to a common vertical conductor} - H10N 70/011: {Manufacture or treatment of multistable switching devices} - H10N 70/021: {Formation of switching materials, e.g. deposition of layers} - H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies} - H10N 70/245: {the species being metal cations, e.g. programmable metallization cells} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8416: {adapted for supplying ionic species} - H10N 70/883: {Oxides or nitrides} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - G11C 11/16: using elements in which the storage effect is based on magnetic spin effect - G11C 2213/15: Current-voltage curve - G11C 2213/55: Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer - G11C 2213/71: Three dimensional array - G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode - G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array. ## Claims ### Claim 1 A semiconductor device comprising: a selector device comprising: a first electrode structure comprising a first material having a first plurality of metal particles, wherein the first material is configured to generate conductive ions of the first plurality of metal particles in response to a first voltage exceeding a first threshold voltage applied to the first electrode structure; a second electrode structure comprising a second material having a second plurality of metal particles, wherein the second material is configured to generate conductive ions of the second plurality of metal particles in response to a second voltage exceeding a second threshold voltage applied to the second electrode structure; and a selector structure comprising a selector material, disposed in contact with and in between the first electrode structure and the second electrode structure, wherein the selector material is configured to allow the conductive ions of the first plurality of metal particles to permeate therein in response to the first voltage applied to the first electrode structure, and wherein the selector material is configured to allow the conductive ions of the second plurality of metal particles to permeate therein in response to the second voltage applied to the second electrode structure; and a two-terminal memory device coupled in series with the selector device. ### Claim 2 (depends on 1) The semiconductor device of claim 1 wherein the two-terminal memory device is selected from a group consisting of: a resistive random access memory (RRAM), a phase-change memory (PCRAM), a magneto-resistive memory (MRAM), a ferroelectric memory (FeRAM), organic memory (ORAM), conductive bridging memory (CBRAM), one-time programmable memory (OTP). ### Claim 3 (depends on 1) The semiconductor device of claim 1 wherein the two-terminal memory comprises a metallic filamentary-based memory device comprising: a conductive layer; a material layer comprising an active metal material having a third plurality of metal particles, wherein the active metal material is configured to generate metallic ions of the third plurality of metal particles in response to a program voltage applied to the two-terminal memory; and a resistive switching media disposed between the conductive layer and the material layer, wherein the resistive switching media comprises a plurality of voids and is configured to allow the metallic ions of the active metal material to permeate and to form a conductive filament therein. ### Claim 4 (depends on 2) The semiconductor device of claim 2 wherein the metallic ions comprise ions of a metal selected from a group consisting of: silver (Ag), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd); and wherein the resistive switching media is selected from a group consisting of: an undoped amorphous silicon material, a non-stoichiometric oxide, SiOx, TaOb (where b is a suitable positive number), HfOc (where c is a suitable positive number), TiOd (where d is a suitable number), and Al2Oe (where e is a suitable positive number). ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the first plurality of metal particles is selected from a group consisting of: Pt, Pd, Ag, Au, Al, Cu, W and Ti; and wherein the selector material is selected from a group consisting of: a non-stoichiometric oxide, a chalcogenide, a solid-electrolyte, and a metal-doped material. ### Claim 6 (depends on 1) The semiconductor device of claim 1 wherein the selector device is characterized by an electrical voltage-current response within a range of 10 mV per decade of current to 100 mV per decade of current. ### Claim 7 (depends on 1) The semiconductor device of claim 1 wherein the selector device is characterized by an electrical voltage-current response within a range of 3.5 mV per decade of current to 14 mV per decade of current. ### Claim 8 (depends on 1) The semiconductor device of claim 1 further comprising: a semiconductor substrate comprising a plurality of CMOS devices; wherein the selector device and the two-terminal memory device are disposed above the semiconductor substrate and operable in conjunction with the plurality of CMOS devices. ### Claim 9 A semiconductor device comprises: a semiconductor substrate; a selector device disposed above the semiconductor substrate, wherein the selector device comprises: a first electrode disposed above the semiconductor substrate, wherein the first electrode comprises a first plurality of metal particles, wherein the first electrode is configured to generate conductive ions of the first plurality of metal particles, in response to a first bias applied across the selector device, wherein a magnitude of the first bias exceeds a magnitude of a first bias threshold; a second electrode disposed above the semiconductor substrate, wherein the second electrode comprises a second plurality of metal particles, wherein the second electrode is configured to generate conductive ions of the second plurality of metal particles, in response to a second bias applied across the selector device, wherein a polarity of the first bias is opposite of a polarity of the second bias; and an insulating material layer disposed adjacent to and in contact with the first electrode and the second electrode, wherein the insulating material layer comprises a selector material having a plurality of defects in absence of a bias being applied across the selector device, wherein the insulating material layer is selected from a group consisting of: an undoped amorphous silicon material, a non-stoichiometric oxide, SiOx, TaOb (where b is a suitable positive number), HfOc (where c is a suitable positive number), TiOd (where d is a suitable number), and Al2Oe (where e is a suitable positive number), wherein the insulating material layer is configured to allow conductive ions of the first plurality of metal particles to occupy first defect locations from the plurality of defects in response to the first bias applied across the selector device, and wherein the insulating material layer is configured to allow conductive ions of the second plurality of metal particles to occupy second defect locations from the plurality of defects in response to the second bias applied across the selector device; and a two-terminal memory disposed above the insulated semiconductor substrate and coupled in series with the selector device. ### Claim 10 (depends on 8) The semiconductor device of claim 8 wherein the two-terminal memory device is selected from a second group consisting of: a resistive random access memory (RRAM), a phase-change memory (PCRAM), a magneto-resistive memory (MRAM), a ferroelectric memory (FeRAM), organic memory (ORAM), conductive bridging memory (CBRAM), and a one-time programmable memory (OTP). ### Claim 11 (depends on 9) The semiconductor device of claim 9 wherein the two-terminal memory comprises a metallic filamentary-based memory device comprising: a conductive layer; a material layer comprising an active metal material having a third plurality of metal particles, wherein the active metal material is configured to generate metallic ions of the third plurality of metal particles in response to a program voltage applied to the two-terminal memory, wherein the metal ions comprise ions of metal selected from a second group consisting of: silver (Ag), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd); and a resistive switching media disposed between the conductive layer and the material layer, wherein the resistive switching media comprises a plurality of voids and is configured to allow the metallic ions of the third plurality of metal particles to permeate and to form a conductive filament therein, wherein the resistive switching media is selected from a third group consisting of: undoped amorphous silicon material, non-stoichiometric oxide, SiOx, TaOb (where b is a suitable positive number), HfOc (where c is a suitable positive number), TiOd (where d is a suitable number), and Al2Oe (where e is a suitable positive number). ### Claim 12 (depends on 9) The semiconductor device of claim 9, wherein the first plurality of metal particles is selected from a second group consisting of: Pt, Pd, Ag, Au, Al, Cu, W and Ti. ### Claim 13 (depends on 9) The semiconductor device of claim 9 further comprising a plurality of CMOS devices disposed upon the semiconductor substrate and coupled to the selector device. ### Claim 14 (depends on 9) The semiconductor device of claim 9 wherein the selector device is characterized by an electrical voltage-current response within a range of 0.01 mV per decade of current to 4 mV per decade of current. ### Claim 15 A method of operating a semiconductor device having a memory device including a selector device and a two-terminal memory component, comprising: applying a first switching voltage of a first polarity to a first terminal of the memory device, the first switching voltage having a magnitude larger than a first threshold voltage associated with the selector device, thereby: generating conductive ions of a first plurality of metal particles in a first electrode of the selector device, disposing the conductive ions of the first plurality of metal particles into first defect locations of a selector material of the selector device that is disposed adjacent to the first electrode, and performing a first memory operation on the two-terminal memory component; and applying a second switching voltage of a second polarity to the first terminal of the memory device, the second switching voltage having a magnitude larger than a second threshold voltage associated with the selector device, thereby: generating conductive ions of a second plurality of metal particles in a second electrode of the selector device, disposing the conductive ions of the second plurality of metal particles into second defect locations of the selector material of the selector device that is disposed adjacent to the second electrode, and performing a second memory operation on the two-terminal memory component. ### Claim 16 (depends on 14) The method of claim 14 wherein the two-terminal memory component is selected from a group consisting of: a resistive random access memory (RRAM), a phase-change memory (PCRAM), a magneto-resistive memory (MRAM), a ferroelectric memory (FeRAM), organic memory (ORAM), conductive bridging memory (CBRAM), one-time programmable memory (OTP); and wherein the first memory operation on the two-terminal memory component is selected from a group consisting of: a read operation and a program operation. ### Claim 17 (depends on 15) The method of claim 15 wherein the second memory operation on the two-terminal memory component comprises an erase operation. ### Claim 18 (depends on 14) The method of claim 14 wherein the performing the first memory operation in response to the first switching voltage comprises: generating metallic ions of an active metal material in a material layer of the two-terminal memory device; and disposing the metallic ions of the active metal material into defect locations of a resistive switching material of the two-terminal memory device that is disposed adjacent to the active metal material, to thereby form a conductive filament within the resistive switching material, in response to the first switching voltage. ### Claim 19 (depends on 17) The method of claim 17 wherein the metallic ions comprise ions of a metal selected from a group consisting of: silver (Ag), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd); and wherein the resistive switching material is selected from a second group consisting of: an undoped amorphous silicon material, a non-stoichiometric oxide, SiOx, TaOb (where b is a suitable positive number), HfOc (where c is a suitable positive number), TiOd (where d is a suitable number), and Al2Oe (where e is a suitable positive number). ### Claim 20 (depends on 14) The method of claim 14 wherein the first plurality of metal particles is selected from a group consisting of: Pt, Pd, Ag, Au, Al, Cu, W and Ti; and wherein the selector material is selected from a second group consisting of: a non-stoichiometric oxide, a chalcogenide, a solid-electrolyte, and a metal-doped material.