# US 10,121,536 B2 · Semiconductor memory device and memory system

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- Number: US 10,121,536 B2
- Document ID: US10121536B2
- Status: Granted
- Kind: B2
- Application number: 15/346,716
- Filed: 2016-11-08
- Published: 2017-12-21
- Granted: 2018-11-06
- Earliest claimed: 2016-06-15
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Weihan Wang; Toshifumi Hashimoto; Noboru Shibata
- Web page: https://patentgrep.com/patent/US10121536B2

## CPC

- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.

## Claims

### Claim 1

A semiconductor memory device comprising:
a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit;
a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit;
a first word line electrically connected to a gate of the first memory cell;
a second word line electrically connected to a gate of the second memory cell;
a first bit line and a second bit line that are connected to the first memory cell and the second memory cell, respectively; and
a first sense amplifier and a second sense amplifier that are connected to the first bit line and the second bit line, respectively, and configured to sense data read from the first bit line and the second bit line in response to a control signal,
wherein in a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell, and the first sense amplifier and the second sense amplifier each receives the control signal during application of the first voltage to the first word line and the second word line, during application of the second voltage to the first word line and the second word line, and during application of the third voltage to the first word line and the second word line.

### Claim 2 (depends on 1)

The device according to claim 1, wherein in each of the first and second memory cells, the first bit is less significant bit than the second bit.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the first voltage is lower than the second voltage, and the second voltage is lower than the third voltage.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the first voltage is higher than the second voltage, and the second voltage is higher than the third voltage.

### Claim 5 (depends on 1)

The device according to claim 1, further comprising:
a first source line and a second source line that are connected to the first memory cell and the second memory cell, respectively,
wherein in the read operation, a fourth voltage is applied to the first source line while the first voltage is applied to the first and second word lines, and a fifth voltage is applied to the second source line while the second voltage is applied to the first and second word lines.

### Claim 6 (depends on 1)

The device according to claim 1, further comprising:
a driver configured to generate a selected word line voltage and a non-selected word line voltage;
a first set of switches that are controlled to supply either the selected word line voltage or the non-selected word line voltage to the first word line; and
a second set of switches that are controlled to supply either the selected word line voltage or the non-selected word line voltage to the second word line.

### Claim 7

A semiconductor memory device comprising:
a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit;
a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit;
a first word line electrically connected to a gate of the first memory cell;
a second word line electrically connected to a gate of the second memory cell;
a first bit line and a second bit line that are connected to the first memory cell and the second memory cell, respectively;
a first sense amplifier that is connected to the first bit line and configured to sense data read from the first bit line in response to a first control signal; and
a second sense amplifier that is connected to the second bit line and configured to sense data read from the second bit line in response to a second control signal different from the first control signal,
wherein in a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell, and the first sense amplifier receives the first control signal during application of the first voltage to the first word line and the second word line, and the second sense amplifier receives the second control signal during application of the second voltage to the first word line and the second word line and during application of the third voltage to the first word line and the second word line.

### Claim 8 (depends on 7)

The device according to claim 7, wherein in each of the first and second memory cells, the first bit is less significant bit than the second bit.

### Claim 9 (depends on 7)

The device according to claim 7, wherein the first voltage is lower than the second voltage, and the second voltage is lower than the third voltage.

### Claim 10 (depends on 7)

The device according to claim 7, wherein the first voltage is higher than the second voltage, and the second voltage is higher than the third voltage.

### Claim 11 (depends on 7)

The device according to claim 7, further comprising:
a first source line and a second source line that are connected to the first memory cell and the second memory cell, respectively,
wherein in the read operation, a fourth voltage is applied to the first source line while the first voltage is applied to the first and second word lines, and a fifth voltage is applied to the second source line while the second voltage is applied to the first and second word lines.

### Claim 12 (depends on 7)

The device according to claim 7, further comprising:
a driver configured to generate a selected word line voltage and a non-selected word line voltage;
a first set of switches that are controlled to supply either the selected word line voltage or the non-selected word line voltage to the first word line; and
a second set of switches that are controlled to supply either the selected word line voltage or the non-selected word line voltage to the second word line.