# US 10,121,533 B2 · Techniques for data retention in memory cells during power interruption

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- Number: US 10,121,533 B2
- Document ID: US10121533B2
- Status: Granted
- Kind: B2
- Application number: 14/965,362
- Filed: 2015-12-10
- Published: 2016-04-07
- Granted: 2018-11-06
- Earliest claimed: 2012-11-21
- Assignees: Nano-Retina, Inc.
- Applicants: Nano-Retina, Inc.
- Inventors: Tuvia Liran
- Web page: https://patentgrep.com/patent/US10121533B2

## CPC

- G11C 11/417: for memory cells of the field-effect type
- G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)}
- H10B 10/12: {comprising a MOSFET load element}
- A61F 2/14: Eye parts, e.g. lenses or corneal implants; Artificial eyes
- A61N 1/36046: {of the eye}
- A61N 1/3787: {from an external energy source}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- A61F: FILTERS IMPLANTABLE INTO BLOOD VESSELS; PROSTHESES; DEVICES PROVIDING PATENCY TO, OR PREVENTING COLLAPSING OF, TUBULAR STRUCTURES OF THE BODY, e.g. STENTS; ORTHOPAEDIC, NURSING OR CONTRACEPTIVE DEVICES; FOMENTATION; TREATMENT OR PROTECTION OF EYES OR EARS; BANDAGES, DRESSINGS OR ABSORBENT PADS; FIRST-AID KITS (dental prosthetics A61C)
- A61N: ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY (measurement of bioelectric currents A61B; surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body A61B18/00; anaesthetic apparatus in general A61M; incandescent lamps H01K; infrared radiators for heating H05B)

## Abstract

Volatile memory is described, comprising: (i) a first inverter comprising a first p-type field effect transistor (FET) connected to a first n-type FET; (ii) a second inverter comprising a second p-type FET connected to a second n-type FET; (iii) a third p-type FET; (iv) a fourth p-type FET; and (v) a floating line connecting (i) a source of the third p-type FET, and (ii) a source of the fourth p-type FET, wherein: (a) the first data line is connected to: a gate of the second p-type FET, a gate of the second n-type FET, a drain of the third p-type FET, and a gate of the fourth p-type FET, and (b) the second data line is connected to: a gate of the first p-type FET, a gate of the first n-type FET, a drain of the fourth p-type FET, and a gate of the third p-type FET.

## Claims

### Claim 1

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:
a first CMOS inverter, having a first input and a first output;
a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
a first PMOS transistor, having a first source, a first gate, and a first drain;
a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
a first connector, electrically connecting:
the first output,
the first drain,
the second gate, and
the second input; and
a second connector, electrically connecting:
the second output,
the second drain,
the first gate, and
the first input,
wherein:
the first PMOS transistor has a first-transistor threshold voltage,
the first CMOS inverter comprises a third PMOS transistor having a third-transistor threshold voltage, and
the first PMOS transistor is configured such that the first-transistor threshold voltage is greater than the third-transistor threshold voltage.

### Claim 2 (depends on 1)

The apparatus according to claim 1, wherein:
the third PMOS transistor has a third source, a third gate, a third drain, and a third-transistor n-well,
the second CMOS inverter comprises a fourth PMOS transistor having a fourth source, a fourth gate, a fourth drain, and a fourth-transistor n-well, and
each memory circuit further comprises a third connector, electrically connecting the first source, the second source, the third-transistor n-well, and the fourth-transistor n-well.

### Claim 3 (depends on 1)

The apparatus according to claim 1, wherein each memory circuit is an SRAM cell.

### Claim 4 (depends on 1)

The apparatus according to claim 1, wherein each memory circuit is a latch.

### Claim 5 (depends on 1)

The apparatus according to claim 1, wherein each memory circuit further comprises a third connector, electrically connecting the first source and the second source, wherein each memory circuit further comprises an electrical capacitive element that comprises a first conductor and a second conductor, and wherein the third connector electrically connects the first source, the second source, and the first conductor.

### Claim 6 (depends on 5)

The apparatus according to claim 5, wherein the electrical capacitive element comprises a distinct capacitor.

### Claim 7 (depends on 1)

The apparatus according to claim 1, wherein each memory circuit further comprises a third connector, electrically connecting the first source and the second source, and wherein the apparatus further comprises a dielectric in electrical contact with the third connector.

### Claim 8 (depends on 7)

The apparatus according to claim 7, wherein the dielectric is a substrate on which the first, second, and third connectors are disposed.

### Claim 9 (depends on 1)

The apparatus according to claim 1, wherein the one or more memory circuits comprises at least a first memory circuit and a second memory circuit, and wherein the apparatus further comprises a third connector, electrically connecting:
the first source of the first memory circuit,
the second source of the first memory circuit,
the first source of the second memory circuit, and
the second source of the second memory circuit.

### Claim 10 (depends on 9)

The apparatus according to claim 9, further comprising an electrical capacitive element that comprises a first conductor and a second conductor, wherein the third connector electrically connects:
the first conductor,
the first source of the first memory circuit,
the second source of the first memory circuit,
the first source of the second memory circuit, and
the second source of the second memory circuit.

### Claim 11 (depends on 10)

The apparatus according to claim 10, wherein the electrical capacitive element comprises a distinct capacitor.

### Claim 12 (depends on 9)

The apparatus according to claim 9, further comprising a dielectric in electrical contact with the third connector.

### Claim 13 (depends on 12)

The apparatus according to claim 12, wherein the dielectric is a substrate on which the first, second, and third connectors are disposed.

### Claim 14 (depends on 1)

The apparatus according to claim 1, wherein the apparatus comprises a medical implant that comprises the device.

### Claim 15 (depends on 14)

The apparatus according to claim 14, wherein the medical implant is an artificial retina implant.

### Claim 16 (depends on 1)

The apparatus according to claim 1, wherein each memory circuit is a six-transistor SRAM cell.

### Claim 17 (depends on 1)

The apparatus according to claim 1, wherein each memory circuit is an eight-transistor SRAM cell.

### Claim 18 (depends on 1)

The apparatus according to claim 1, wherein each memory circuit is a ten-transistor SRAM cell.

### Claim 19 (depends on 1)

The apparatus according to claim 1, wherein the first PMOS transistor is configured such that the first-transistor threshold voltage is greater than the third-transistor threshold voltage by between 0.05 and 0.2 V.

### Claim 20

A Static Random Access Memory (SRAM) device, comprising one or more SRAM cells, each SRAM cell comprising:
a first CMOS inverter, having a first input and a first output;
a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
a first PMOS transistor, having a first source, a first gate, and a first drain;
a second PMOS transistor, having a second source, a second gate, and a second drain;
an electrical capacitive element, comprising a first conductor and a second conductor;
a first connector, electrically connecting:
the first output,
the first drain,
the second gate, and
the second input;
a second connector, electrically connecting:
the second output,
the second drain,
the first gate, and
the first input; and
a third connector, electrically connecting:
the first source,
the second source, and
the first conductor.

### Claim 21

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:
a first CMOS inverter, having a first input and a first output;
a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
a first PMOS transistor, having a first source, a first gate, and a first drain;
a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
a first connector, electrically connecting:
the first output,
the first drain,
the second gate, and
the second input; and
a second connector, electrically connecting:
the second output,
the second drain,
the first gate, and
the first input,
wherein each memory circuit further comprises a third connector, electrically connecting the first source and the second source, wherein each memory circuit further comprises an electrical capacitive element that comprises a first conductor and a second conductor, and wherein the third connector electrically connects the first source, the second source, and the first conductor.

### Claim 22 (depends on 21)

The apparatus according to claim 21, wherein the electrical capacitive element comprises a distinct capacitor.

### Claim 23 (depends on 18)

The apparatus according to claim 18, wherein:
the first PMOS transistor has a first-transistor threshold voltage,
the first CMOS inverter comprises a third PMOS transistor having a third-transistor threshold voltage, and
the first PMOS transistor is configured such that the first-transistor threshold voltage is greater than the third-transistor threshold voltage.

### Claim 24

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:
a first CMOS inverter, having a first input and a first output;
a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
a first PMOS transistor, having a first source, a first gate, and a first drain;
a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
a first connector, electrically connecting:
the first output,
the first drain,
the second gate, and
the second input; and
a second connector, electrically connecting:
the second output,
the second drain,
the first gate, and
the first input,
wherein each memory circuit further comprises a third connector, electrically connecting the first source and the second source, and wherein the apparatus further comprises a dielectric in electrical contact with the third connector.

### Claim 25 (depends on 24)

The apparatus according to claim 24, wherein the dielectric is a substrate on which the first, second, and third connectors are disposed.

### Claim 26

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:
a first CMOS inverter, having a first input and a first output;
a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
a first PMOS transistor, having a first source, a first gate, and a first drain;
a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
a first connector, electrically connecting:
the first output,
the first drain,
the second gate, and
the second input; and
a second connector, electrically connecting:
the second output,
the second drain,
the first gate, and
the first input,
wherein:
the one or more memory circuits comprises at least a first memory circuit and a second memory circuit,
the apparatus further comprises a third connector, electrically connecting:
the first source of the first memory circuit,
the second source of the first memory circuit,
the first source of the second memory circuit, and
the second source of the second memory circuit,
the apparatus further comprises an electrical capacitive element that comprises a distinct capacitor that comprises a first conductor and a second conductor,
the third connector electrically connects:
the first conductor,
the first source of the first memory circuit,
the second source of the first memory circuit,
the first source of the second memory circuit, and
the second source of the second memory circuit, and
the electrical capacitive element comprises a distinct capacitor.

### Claim 27

Apparatus comprising a volatile memory device comprising one or more memory circuits, each memory circuit comprising:
a first CMOS inverter, having a first input and a first output;
a second CMOS inverter, cross-coupled to the first CMOS inverter, and having a second input and a second output;
a first PMOS transistor, having a first source, a first gate, and a first drain;
a second PMOS transistor, having a second source electrically connected to the first source, a second gate, and a second drain;
a first connector, electrically connecting:
the first output,
the first drain,
the second gate, and
the second input; and
a second connector, electrically connecting:
the second output,
the second drain,
the first gate, and
the first input,
wherein:
the one or more memory circuits comprises at least a first memory circuit and a second memory circuit, and wherein the apparatus further comprises a third connector, electrically connecting:
the first source of the first memory circuit,
the second source of the first memory circuit,
the first source of the second memory circuit, and
the second source of the second memory circuit, and
the apparatus further comprises a dielectric in electrical contact with the third connector.