# US 10,121,531 B2 · Semiconductor memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,531 B2
- Document ID: US10121531B2
- Status: Granted
- Kind: B2
- Application number: 15/795,784
- Filed: 2017-10-27
- Published: 2018-05-03
- Granted: 2018-11-06
- Earliest claimed: 2016-10-28
- Assignees: Lapis Semiconductor Co., Ltd.
- Applicants: LAPIS Semiconductor Co., Ltd.
- Inventors: Takashi Yamada
- Web page: https://patentgrep.com/patent/US10121531B2

## CPC

- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 5/10: for interconnecting capacitors
- G11C 7/02: with means for avoiding parasitic signals
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/2259: {Cell access}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory includes j×k first memory cells, j upper bit lines, (½)j sense amplifiers, j×k lower first bit lines, k first word lines, k pairs of plate lines, each pair having first and second plate lines, each being connected to odd-numbered and even-numbered first memory cells of one of the k columns, a pair of discharge signal lines having a first discharge signal line and a second discharge signal line respectively connecting two of the j upper lines in each sense amplifier to a prescribed potential, j×m second memory cells, j lower second bit lines, m second word lines, m third plate lines each connected to the j second memory cells of one of the m columns, and j shield lines each provided at positions respectively corresponding to the j upper bit lines, which are parallel to one another.

## Claims

### Claim 1

A semiconductor memory having a first memory region and a second memory region, comprising:
j×k first memory cells arranged in j rows and k columns in the first memory region, j being a positive even number, k being a natural number;
j upper bit lines each connected to the k first memory cells of a corresponding one of the j rows;
(½)j sense amplifiers each connected to two of the j upper bit lines;
j×k lower first bit lines connected respectably to the j×k first memory cells, each of k of the j×k lower first bit lines connected to memory cells of one of the j rows being connected to a corresponding one of the j upper bit lines;
k first word lines each connected to the j first memory cells of a corresponding one of the k columns;
k pairs of plate lines, each pair having a first plate line and a second plate line, each said first plate line being connected to odd-numbered first memory cells of a corresponding one of the k columns, each said second plate line being connected to even-numbered first memory cells of a corresponding one of the k columns;
a pair of discharge signal lines having
a first discharge signal line, and
a second discharge signal line respectively connecting the two of the j upper bit lines in each sense amplifier to a prescribed potential;
j×m second memory cells arranged in j rows and m columns in the second memory region, the m second memory cells of a same row being connected to a corresponding one of the j upper bit lines, m being a natural number;
j lower second bit lines each corresponding to one of the j upper bit lines;
m second word lines each connected to the j second memory cells of a corresponding one of the m columns;
m third plate lines each connected to the j second memory cells of a corresponding one of the m columns; and
j shield lines each provided at positions respectively corresponding to the j upper bit lines and respectively adjacent to the j lower second bit lines, which are parallel to one another.

### Claim 2 (depends on 1)

The semiconductor memory according to claim 1, wherein
each first memory cell includes
a first memory cell transistor connected to one of the lower first bit lines, and
a first ferroelectric capacitor connected to one of the first plate lines and the second plate lines, and
each second memory cell includes
a second memory cell transistor connected to another one of the lower second bit lines, and
a second ferroelectric capacitor connected to one of the m plate lines.

### Claim 3 (depends on 1)

The semiconductor memory according to claim 1, wherein the prescribed potential is ground potential.

### Claim 4 (depends on 1)

The semiconductor memory according to claim 1, wherein the j shield lines are connected to a ground potential.

### Claim 5 (depends on 1)

The semiconductor memory according to claim 1, wherein the j upper bit lines and the j shield lines are disposed in a same wiring layer.

### Claim 6 (depends on 1)

The semiconductor memory according to claim 1, wherein each of the first memory cells includes a bit line discharge transistor that is connected to one of the lower first bit lines and connects the one of first bit lines connected there to the ground potential.

### Claim 7 (depends on 1)

The semiconductor memory according to claim 1, wherein
each of the third plate lines is connected to the second memory cells in odd-numbered rows of a corresponding one of the m columns, and
the second memory region further includes m fourth plate lines each connected to the second memory cells in even-numbered rows of a corresponding one of the m columns.

### Claim 8 (depends on 1)

The semiconductor memory according to claim 1, wherein the second memory region is disposed on a far end of the (½)j sense amplifiers of the first memory region.

### Claim 9 (depends on 1)

The semiconductor memory according to claim 1, the j upper bit lines and the j×k lower first bit lines, the j lower second bit lines and the j shield lines are disposed in a same wiring layer.

### Claim 10

A semiconductor memory having a first memory region and a second memory region, comprising:
j×k first memory cells arranged in j rows and k columns in the first memory region, j being a positive even number, k being a natural number;
j upper bit lines each connected to the k first memory cells of a corresponding one of the j rows;
(½)j sense amplifiers each connected to two of the j upper bit lines;
j×k lower first bit lines connected respectably to the j×k first memory cells;
k pairs of word lines, each pair having a first word line and a second word line, each said first word line being connected to odd-numbered first memory cells of a corresponding one of the k columns, each said second word line being connected to even-numbered first memory cells of the corresponding one of the k columns;
a pair of discharge signal lines having
a first discharge signal line, and
a second discharge signal line selectively connecting the two of the j upper bit lines in each sense amplifier to a prescribed potential;
j×m second memory cells arranged in j rows and m columns in the second memory region, the m second memory cells in a same row being connected to a corresponding one of the j upper bit lines, m being a natural number;
j lower second bit lines each corresponding to one of the j upper bit lines;
m third word lines each connected to the j second memory cells of a corresponding one of the m columns; and
j shield lines each provided at positions respectively corresponding to the j upper bit lines and respectively adjacent to the j lower second bit lines, which are parallel to one another.