# US 10,121,530 B2 · Implementing eFuse visual security of stored data using EDRAM

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- Number: US 10,121,530 B2
- Document ID: US10121530B2
- Status: Granted
- Kind: B2
- Application number: 15/587,713
- Filed: 2017-05-05
- Published: 2017-08-17
- Granted: 2018-11-06
- Earliest claimed: 2015-11-23
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Todd A. Christensen; Karl R. Erickson; Phil C. Paone; David P. Paulsen; John E. Sheets, II; Gregory J. Uhlmann
- Web page: https://patentgrep.com/patent/US10121530B2

## CPC

- G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52)
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 17/16: using electrically-fusible links
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuitry having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

## Claims

### Claim 1

A method for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), said method comprising:
providing an EDRAM;
providing an eFuse having an initial state of a logical 0; said EDRAM and said eFuse having a same bit count; and
providing an exclusive OR (XOR) gate receiving respective outputs of said eFuse and said EDRAM, said XOR gate providing an output data combination enabling EDRAM random data to be known at wafer test; and enabling said eFuse to be programmed to provide any logical value out of the output data combination, generating a control signal indicating EDRAM data ready for being read with filtering by said eFuse via said XOR gate.

### Claim 2 (depends on 1)

The method as recited in claim 1 includes generating said control signal using a busy signal from said eFuse to indicate that an eFuse read has not completed.

### Claim 3 (depends on 1)

The method as recited in claim 1 wherein said eFuse has a busy signal used to indicate that an eFuse read has not completed, and includes using said eFuse busy signal to provide said control signal for reading said XOR gate.

### Claim 4 (depends on 1)

The method as recited in claim 1 includes providing a capture latch receiving respective outputs of said XOR gate, said capture latch receiving said control signal for reading said XOR gate.