# US 10,121,528 B2 · Apparatus, method and system for providing termination for multiple chips of an integrated circuit package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,528 B2 - Document ID: US10121528B2 - Status: Granted - Kind: B2 - Application number: 14/440,068 - Filed: 2013-11-22 - Published: 2015-10-01 - Granted: 2018-11-06 - Earliest claimed: 2012-11-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: George Vergis; Kuljit S. Bains; James A. McCall; Ge Chang - Web page: https://patentgrep.com/patent/US10121528B2 ## CPC - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0637: {Permissions} - G06F 3/0673: {Single storage device} - G06F 13/1663: {Access to shared memory} - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/109: {Control signal input circuits} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 11/408: Address circuits - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series. ## Claims ### Claim 1 An integrated circuit (IC) package comprising: a command and address bus; a plurality of stacked memory chips each coupled to the command and address bus, each of the plurality of stacked memory chips including a respective on-die termination control circuit of a plurality of on-die termination control circuits coupled to the command and address bus, wherein a first memory chip of the plurality of stacked memory chips includes a first on-die termination control circuit of the plurality of on-die termination control circuits, wherein, for each of the plurality of on-die termination control circuits: a respective first termination state of the on-die termination control circuit is to provide termination with the on-die termination control circuit; and a respective second termination state of the on-die termination control circuit is to prevent any termination from being provided with the on-die termination control circuit; wherein, only the first on-die termination control circuit is to selectively provide termination to the command and address bus, wherein, of the plurality of on-die termination circuits: the first on-die termination control circuit is farthest away from the inputs/outputs (I/Os) of the IC package than the remaining other on-die termination control circuits of the memory chips other than the first memory chip; and only the first on-die termination control circuit is coupled to enable an ability to selectively transition, responsive to a termination control signal, between the respective first termination state and the respective second termination state; and, the remaining other on die termination control circuits of the memory chips other than the first memory chip are to be in a deterministic termination state that is not responsive to the termination control signal and does not terminate the command and address bus. ### Claim 2 (depends on 1) The IC package of claim 1, wherein the plurality of stacked memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series. ### Claim 3 (depends on 2) The IC package of claim 2, wherein the first memory chip is a last memory chip in a series of all memory chips coupled to the command and address bus. ### Claim 4 (depends on 1) The IC package of claim 1, wherein, the remaining other on die termination control circuits of the memory chips other than the first memory chip are hardwired to a supply voltage line. ### Claim 5 (depends on 1) The IC package of claim 1, wherein the plurality of stacked memory chips include one or more dynamic random access memory (DRAM) chips. ### Claim 6 A system comprising: a memory controller; an interconnect coupled to receive command and address signals from the memory controller; and an integrated circuit (IC) package coupled to receive the command and address signals from the interconnect, the IC package including: a command and address bus; a plurality of stacked memory chips each coupled to the command and address bus, each of the plurality of stacked memory chips including a respective on-die termination control circuit of a plurality of on-die termination control circuits coupled to the command and address bus, wherein a first memory chip of the plurality of stacked memory chips includes a first on-die termination control circuit of the plurality of on-die termination control circuits, wherein, for each of the plurality of on-die termination control circuits: a respective first termination state of the on-die termination control circuit is to provide termination with the on-die termination control circuit; and a respective second termination state of the on-die termination control circuit is to prevent any termination from being provided with the on-die termination control circuit; wherein, only the first on-die termination control circuit is to selectively provide termination to the command and address bus, wherein, of the plurality of on-die termination circuits: the first on-die termination control circuit is farthest away from the inputs/outputs (I/Os) of the IC package than the remaining other on-die termination control circuits of the memory chips other than the first memory chip; and only the first on-die termination control circuit is coupled to enable an ability to selectively transition, responsive to a termination control signal, between the respective first termination state and the respective second termination state; and, the remaining other on die termination control circuits of the memory chips other than the first memory chip are to be in a deterministic termination state that is not responsive to the termination control signal and does not terminate the command and address bus. ### Claim 7 (depends on 6) The system of claim 6, wherein the plurality of stacked memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series. ### Claim 8 (depends on 7) The system of claim 7, wherein the first memory chip is a last memory chip in a series of all memory chips of the IC package coupled to the command and address bus. ### Claim 9 (depends on 6) The system of claim 6, wherein, the remaining other on die termination control circuits of the memory chips other than the first memory chip are hardwired to a supply voltage line. ### Claim 10 (depends on 6) The system of claim 6, wherein the plurality of stacked memory chips include one or more dynamic random access memory (DRAM) chips.