# US 10,121,525 B2 · Nonvolatile memory device and operating method of the same

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- Number: US 10,121,525 B2
- Document ID: US10121525B2
- Status: Granted
- Kind: B2
- Application number: 15/793,497
- Filed: 2017-10-25
- Published: 2018-07-12
- Granted: 2018-11-06
- Earliest claimed: 2017-01-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yong Jun Lee
- Web page: https://patentgrep.com/patent/US10121525B2

## CPC

- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2213/72: Array wherein the access device being a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A nonvolatile memory device includes memory banks and write block circuits. Each of the memory banks includes an array of memory cells. Each of the memory cells is disposed in a region of the memory banks in which bit lines and word lines intersect. The write block circuits are connected to the memory banks. Each of the write block circuits includes write drivers, that are each connected to the bit lines. The write block circuits provide a write current of the memory cells to the bit lines. A total number of write block circuits is used to determine the number of memory banks that are simultaneously provided with a write command from a host. A total number of write drivers that are activated is based on a predetermined reference value.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a plurality of memory banks each of which comprising a memory cell array including a plurality of memory cells, each of the plurality of memory cells being disposed in regions of the plurality of memory banks in which a plurality of bit lines and a plurality of word lines intersect with each other; and
a plurality of write block circuits connected to the plurality of memory banks, wherein each of the write block circuits of the plurality of write block circuits comprises a plurality of write drivers, connected to the plurality of bit lines, and providing a write current of the memory cells to the bit lines,
wherein a total number of write block circuits of the plurality of write block circuits, is used to determine a number of memory banks, of the plurality of memory banks, that are simultaneously provided with a write command from a host, and
wherein a total number of write drivers of the plurality of write drivers that are activated is based on a predetermined reference value.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein the plurality of write block circuits activates write drivers of the plurality of write drivers having the predetermined reference value, when each of the plurality of memory devices is in an idle state, and when the write command is provided to the plurality of memory banks.

### Claim 3 (depends on 2)

The nonvolatile memory device of claim 2, wherein the predetermined reference value is determined, based on an amount of a maximum power required at the time of the writing operation of the nonvolatile memory device.

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, wherein the plurality of memory banks comprises first to m-th memory banks (where m is an integer greater or equal to 2), and
the plurality of write block circuits comprises first to m-th write block circuits each connected to correspond to the plurality of memory banks.

### Claim 5 (depends on 4)

The nonvolatile memory device of claim 4, wherein the first to m-th write block circuits comprise first to n-th write drivers (where n is an integer greater than or equal to 2), and
when the write command from the host is directed to the k memory banks, each of the write block circuits activates max/k (where max is the predetermined reference value) write drivers among the n write drivers.

### Claim 6 (depends on 4)

The nonvolatile memory device of claim 4, wherein the number of write drivers simultaneously activated in the plurality of write blocks does not exceed the predetermined reference value.

### Claim 7 (depends on 1)

The nonvolatile memory device of claim 1, wherein the plurality of write block. circuits reduces the number of the activated write blocks, when the number of memory banks simultaneously provided with the write command from the host increases.

### Claim 8 (depends on 1)

The nonvolatile memory device of claim 1, wherein the memory cell comprises a resistive memory cell.

### Claim 9 (depends on 8)

The nonvolatile memory device of claim 8, wherein the plurality of memory banks comprises a variable resistance element connected to the memory cell, and an access element for controlling a current flowing through the variable resistance element.

### Claim 10 (depends on 1)

The nonvolatile memory device of claim 1, wherein a clock signal is provided from the host to the memory bank, and
the memory bank executes the write command in synchronization with the clock signal.

### Claim 11

A method of operating a. nonvolatile memory, the method comprising:
providing write commands to a plurality of memory banks;
determining whether the write command provided to the plurality of memory banks is simultaneously provided to each memory bank of the plurality of memory banks; and
controlling a plurality of write block circuits, connected to the plurality of memory banks, based on the determined result,
wherein each of the plurality of write block circuits comprise a plurality of write drivers which provides a write current to the plurality of memory banks, and
controlling the plurality of write block circuits comprises:
determining a number of memory banks, of the plurality of memory banks, that are simultaneously provided with the write command, and determining a number of the plurality of write drivers that are activated based on a predetermined reference value.

### Claim 12 (depends on 11)

The method of claim 11, wherein determining the number of the plurality of write drivers that are activated comprises:
reducing the number of the activated write blocks, when the number of memory banks simultaneously provided with the write command from the host increases.

### Claim 13 (depends on 11)

The method of claim 11, wherein determining the number of the plurality of write drivers that are activated comprises:
determining whether all the plurality of memory devices are in an idle state, when the write command is provided to the memory bank, and
activating the write drivers having the predetermined reference value.

### Claim 14 (depends on 11)

The method of claim 11, wherein the number of the plurality of write block circuits is equal to the number of the plurality of memory banks.

### Claim 15

A. non-volatile memory device, comprising:
a plurality of memory banks, each including an array of phase change memory cells divided into a plurality of blocks; and
a plurality of write drivers for writing to the phase change memory cells of the plurality of memory banks,
wherein a maximum number of blocks of the plurality of blocks that are simultaneously written to by the plurality of write drivers is determined based on a number of phase change memory cells, of the plurality of memory banks, that is in an idle state.

### Claim 16 (depends on 15)

The non-volatile memory device of claim 15, wherein as the number of phase change memory cells, of the plurality of memory banks, that is in the idle state increases, the number of blocks that are simultaneously written to by the plurality of write drivers increases.

### Claim 17 (depends on 15)

The non-volatile memory device of claim 15, wherein a maximum number of write drivers, of the plurality write drivers, that simultaneously write to phase change memory cells, of the plurality of memory banks, is constant irrespective of a number of blocks that are simultaneously written to by the plurality of write drivers.

### Claim 18 (depends on 15)

The non-volatile memory device of claim 15, wherein the array of phase change memory cells is defined by a matrix of bit lines intersecting word lines.

### Claim 19 (depends on 18)

The non-volatile memory device of claim 18, wherein each of the plurality of write drivers is connected to an intersection of a bit line and a word line.

### Claim 20 (depends on 15)

The non-volatile memory device of claim 15, wherein each phase change memory cell includes a variable resistance element, a phase change material, and an access element for controlling a current through the variable resistance element.