# US 10,121,524 B1 · Semiconductor devices

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- Number: US 10,121,524 B1
- Document ID: US10121524B1
- Status: Granted
- Kind: B1
- Application number: 15/828,974
- Filed: 2017-12-01
- Granted: 2018-11-06
- Earliest claimed: 2017-07-19
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Chang Hyun Kim
- Web page: https://patentgrep.com/patent/US10121524B1

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/109: {Control signal input circuits}
- G11C 2207/2272: Latency related aspects
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device includes a command input circuit and an internal command generation circuit. The command input circuit is synchronized with a clock signal to generate an input command which is enabled if an external command is inputted to the command input circuit. The internal command generation circuit delays the input command by a predetermined period according to a latency information signal to generate an internal command, in synchronization with a first division clock signal and a second division clock signal generated by division of a frequency of the clock signal. The predetermined period is set to be equal to a sum of a first delay amount corresponding to “N” times a cycle time of the second division clock signal and a second delay amount corresponding to “M” times a cycle time of the clock signal.

## Claims

### Claim 1

A semiconductor device comprising:
a command input circuit configured to be synchronized with a clock signal to generate an input command which is enabled if an external command is inputted to the command input circuit; and
an internal command generation circuit configured to delay the input command by a predetermined period according to a latency information signal to generate an internal command, in synchronization with a first division clock signal and a second division clock signal generated by division of a frequency of the clock signal,
wherein the predetermined period is set to be equal to a sum of a first delay amount corresponding to “N” times a cycle time of the second division clock signal and a second delay amount corresponding to “M” times a cycle time of the clock signal.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein the first division clock signal has a frequency which is one (2N)th a frequency of the clock signal; and
wherein the second division clock signal has a frequency which is one (2N)th a frequency of the first division clock signal.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the numbers “N” and “M” are natural numbers.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the latency information signal includes a first group and a second group;
wherein the first group of the latency information signal is a signal for setting the second delay amount; and
wherein the second group of the latency information signal is a signal for setting the first delay amount.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the internal command generation circuit includes:
a selection command generation circuit configured to delay the input command by the predetermined period according to the latency information signal in synchronization with the first and second division clock signals to generate a plurality of selection commands; and
a selection/transmission circuit configured to detect a time that the external command is inputted and configured to output any one of the plurality of selection commands as the internal command according to the detection result.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the selection command generation circuit includes:
a control signal generation circuit configured to decode the latency information signal to generate a plurality of control signals, one of which is selectively enabled;
a shifting circuit configured to delay the input command by the first delay amount to generate a first shift command, in response to the plurality of control signals;
a pulse width control circuit configured to control a pulse width of the first shift command in synchronization with the clock signal, the first division clock signal, and the second division clock signal to generate a second shift command; and
a selection command output circuit configured to delay the second shift command by the second delay amount to output the delayed second shift command as any one of the plurality of selection commands, in response to an enablement signal generated from the latency information signal.

### Claim 7 (depends on 6)

The semiconductor device of claim 6,
wherein the plurality of control signals include a first control signal, a second control signal, and a third control signal; and
wherein the shifting circuit includes:
a first delay circuit configured to delay the input command by one cycle time of the second division clock signal to generate a first delayed command, in response to the first control signal;
a second delay circuit configured to delay the input command or the first delayed command by one cycle time of the second division clock signal to generate a second delayed command, in response to the second control signal; and
a third delay circuit configured to delay the input command or the second delayed command by one cycle time of the second division clock signal to generate the first shift command, in response to the third control signal.

### Claim 8 (depends on 6)

The semiconductor device of claim 6,
wherein the enablement signal includes first to fourth enablement signals;
wherein the plurality of selection commands include first to fourth selection commands; and
wherein the selection command output circuit includes:
a first output circuit configured to be synchronized with the clock signal to output the second shift command as the first selection command, in response to the first enablement signal;
a second output circuit configured to be synchronized with the clock signal to output the first selection command as the second selection command, in response to the second enablement signal;
a third output circuit configured to be synchronized with the clock signal to output the second selection command as the third selection command, in response to the third enablement signal; and
a fourth output circuit configured to be synchronized with the clock signal to output the third selection command as the fourth selection command, in response to the fourth enablement signal.

### Claim 9 (depends on 5)

The semiconductor device of claim 5, wherein the selection/transmission circuit includes:
a comparison circuit configured to subtract the phase signal, which is generated from the first and second division clock signals, from the latency information signal to generate a plurality of enablement signals, according to a time that the external command is inputted; and
an internal command output circuit configured to output any one of the plurality of selection commands as the internal command in response to the plurality of enablement signals.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the comparison circuit includes:
a phase difference signal generation circuit configured to generate a complementary signal of the phase signal and configured to add the complementary signal of the phase signal to the latency information signal to generate a phase difference signal; and
a decoder configured to decode the phase difference signal to generate the plurality of enablement signals.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the phase difference signal generation circuit includes:
a buffer configured to invert the phase signal to generate an inverted phase signal;
a first logic circuit configured to add a binary number of ‘1’ to the inverted phase signal to generate a summation signal; and
a second logic circuit configured to add the summation signal to the latency information signal to generate the phase difference signal.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the comparison circuit includes:
a phase difference signal generation circuit configured to generate a complementary signal of the latency information signal and configured to add the complementary signal of the latency information signal to the phase signal to generate a phase difference signal; and
a decoder configured to decode the phase difference signal to generate the plurality of enablement signals.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the phase difference signal generation circuit includes:
a buffer configured to invert the latency information signal to generate an inverted latency information signal;
a first logic circuit configured to add a binary number of ‘1’ to the inverted latency information signal to generate a summation signal; and
a second logic circuit configured to add the summation signal to the phase signal to generate the phase difference signal.

### Claim 14

A semiconductor device comprising:
a selection command generation circuit configured to delay an input command generated from an external command by a predetermined period according to a latency information signal to generate a plurality of selection commands, in synchronization with a first division clock signal and a second division clock signal generated by division of a frequency of a clock signal; and
a selection/transmission circuit configured to detect a time that the external command is inputted and configured to output any one of the plurality of selection commands as an internal command according to the detection result,
wherein the predetermined period is set to be equal to a sum of a first delay amount corresponding to “N” times a cycle time of the second division clock signal and a second delay amount corresponding to “M” times a cycle time of the clock signal.

### Claim 15 (depends on 14)

The semiconductor device of claim 14,
wherein the first division clock signal has a frequency which is one (2N)th a frequency of the clock signal; and
wherein the second division clock signal has a frequency which is one (2N)th a frequency of the first division clock signal.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the numbers “N” and “M” are natural numbers.

### Claim 17 (depends on 14)

The semiconductor device of claim 14,
wherein the latency information signal includes a first group and a second group;
wherein the first group of the latency information signal is a signal for setting the second delay amount; and
wherein the second group of the latency information signal is a signal for setting the first delay amount.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the selection command generation circuit includes:
a control signal generation circuit configured to decode the latency information signal to generate a plurality of control signals, one of which is selectively enabled;
a shifting circuit configured to delay the input command by the first delay amount to generate a first shift command, in response to the plurality of control signals;
a pulse width control circuit configured to control a pulse width of the first shift command in synchronization with the clock signal, the first division clock signal, and the second division clock signal to generate a second shift command; and
a selection command output circuit configured to delay the second shift command by the second delay amount to output the delayed second shift command as any one of the plurality of selection commands, in response to an enablement signal generated from the latency information signal.

### Claim 19 (depends on 18)

The semiconductor device of claim 18,
wherein the plurality of control signals include a first control signal, a second control signal, and a third control signal; and
wherein the shifting circuit includes:
a first delay circuit configured to delay the input command by one cycle time of the second division clock signal to generate a first delayed command, in response to the first control signal;
a second delay circuit configured to delay the input command or the first delayed command by one cycle time of the second division clock signal to generate a second delayed command, in response to the second control signal; and
a third delay circuit configured to delay the input command or the second delayed command by one cycle time of the second division clock signal to generate the first shift command, in response to the third control signal.

### Claim 20 (depends on 18)

The semiconductor device of claim 18,
wherein the enablement signal includes first to fourth enablement signals;
wherein the plurality of selection commands include first to fourth selection commands; and
wherein the selection command output circuit includes:
a first output circuit configured to be synchronized with the clock signal to output the second shift command as the first selection command, in response to the first enablement signal;
a second output circuit configured to be synchronized with the clock signal to output the first selection command as the second selection command, in response to the second enablement signal;
a third output circuit configured to be synchronized with the clock signal to output the second selection command as the third selection command, in response to the third enablement signal; and
a fourth output circuit configured to be synchronized with the clock signal to output the third selection command as the fourth selection command, in response to the fourth enablement signal.

### Claim 21 (depends on 14)

The semiconductor device of claim 14, wherein the selection/transmission circuit includes:
a comparison circuit configured to subtract the phase signal, which is generated from the first and second division clock signals, from the latency information signal to generate a plurality of enablement signals, according to a time that the external command is inputted; and
an internal command output circuit configured to output any one of the plurality of selection commands as the internal command in response to the plurality of enablement signals.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein the comparison circuit includes:
a phase difference signal generation circuit configured to generate a complementary signal of the phase signal and configured to add the complementary signal of the phase signal to the latency information signal to generate a phase difference signal; and
a decoder configured to decode the phase difference signal to generate the plurality of enablement signals.

### Claim 23 (depends on 22)

The semiconductor device of claim 22, wherein the phase difference signal generation circuit includes:
a buffer configured to invert the phase signal to generate an inverted phase signal;
a first logic circuit configured to add a binary number of ‘1’ to the inverted phase signal to generate a summation signal; and
a second logic circuit configured to add the summation signal to the latency information signal to generate the phase difference signal.

### Claim 24 (depends on 21)

The semiconductor device of claim 21, wherein the comparison circuit includes:
a phase difference signal generation circuit configured to generate a complementary signal of the latency information signal and configured to add the complementary signal of the latency information signal to the phase signal to generate a phase difference signal; and
a decoder configured to decode the phase difference signal to generate the plurality of enablement signals.

### Claim 25 (depends on 24)

The semiconductor device of claim 24, wherein the phase difference signal generation circuit includes:
a buffer configured to invert the latency information signal to generate an inverted latency information signal;
a first logic circuit configured to add a binary number of ‘1’ to the inverted latency information signal to generate a summation signal; and
a second logic circuit configured to add the summation signal to the phase signal to generate the phase difference signal.