# US 10,121,520 B2 · Memory array and method of forming the same

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- Number: US 10,121,520 B2
- Document ID: US10121520B2
- Status: Granted
- Kind: B2
- Application number: 15/960,815
- Filed: 2018-04-24
- Published: 2018-08-23
- Granted: 2018-11-06
- Earliest claimed: 2013-10-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Hao Hu; Yi-Tzu Chen; Hao-I Yang; Cheng-Jen Chang; Geng-Cing Lin
- Web page: https://patentgrep.com/patent/US10121520B2

## CPC

- G11C 5/144: {Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby}
- G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 11/412: using field-effect transistors only
- G11C 11/419: Read-write [R-W] circuits
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.

## Claims

### Claim 1

A memory array comprising:
a first column of memory cells comprising:
a first bit line;
a first word line; and
a first bit line bar;
a first pre-charge circuit coupled to the first bit line;
a second pre-charge circuit coupled to the first bit line bar;
a second column of memory cells comprising:
the first bit line bar;
a second word line; and
a second bit line; and
a set of input output circuits;
wherein the first column of memory cells and the second column of memory cells are configured to share the first bit line bar;
the first bit line and the first bit line bar are in a first plane; and
at least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.

### Claim 2 (depends on 1)

The memory array of claim 1, wherein the first pre-charge circuit comprises:
a first transistor of a first type comprising:
a first terminal of the first transistor;
a second terminal of the first transistor being coupled to the first bit line; and
a third terminal of the first transistor being coupled to at least a first supply voltage; and
the second pre-charge circuit comprises:
a second transistor of the first type comprising:
a first terminal of the second transistor being coupled to at least the first terminal of the first transistor;
a second terminal of the second transistor being coupled to the first bit line bar; and
a third terminal of the second transistor being coupled to the first supply voltage and the third terminal of the first transistor.

### Claim 3 (depends on 2)

The memory array of claim 2, wherein the second pre-charge circuit further comprises:
a third transistor of the first type comprising:
a first terminal of the third transistor being coupled to the first terminal of the first transistor and the first terminal of the second transistor;
a second terminal of the third transistor being coupled to the second bit line; and
a third terminal of the third transistor being coupled to the first supply voltage, the third terminal of the first transistor and the third terminal of the second transistor.

### Claim 4 (depends on 3)

The memory array of claim 3, wherein the first type is a P-type.

### Claim 5 (depends on 1)

The memory array of claim 1, further comprising:
a third column of memory cells comprising:
the second bit line;
a third word line; and
a second bit line bar; and
a fourth column of memory cells comprising:
the second bit line bar;
a fourth word line; and
a third bit line,
wherein the third column of memory cells and the second column of memory cells are configured to share the second bit line; and
the third column of memory cells and the fourth column of memory cells are configured to share the second bit line bar.

### Claim 6 (depends on 5)

The memory array of claim 5, wherein
the second bit line bar and the third bit line are in the first plane; and
at least a portion of the third word line and at least a portion of the fourth word line are in the second plane.

### Claim 7 (depends on 1)

The memory array of claim 1, further comprising:
a pull-up circuit coupled to the first bit line and the first bit line bar, and configured to pull the first bit line or the first bit line bar towards a first supply voltage.

### Claim 8 (depends on 7)

The memory array of claim 7, wherein the pull-up circuit comprises:
a first transistor of a first type comprising:
a first terminal of the first transistor being coupled to at least the first bit line bar;
a second terminal of the first transistor being coupled to at least the first bit line; and
a third terminal of the first transistor being coupled to the first supply voltage; and
a second transistor of the first type comprising:
a first terminal of the second transistor being coupled to the second terminal of the first transistor and the first bit line;
a second terminal of the second transistor being coupled to the first bit line bar and the first terminal of the first transistor; and
a third terminal of the second transistor being coupled to the first supply voltage.

### Claim 9 (depends on 1)

The memory array of claim 1, wherein the second plane is substantially orthogonal to the first plane.

### Claim 10 (depends on 1)

The memory array of claim 1, wherein the set of input output circuits comprises:
a first data line;
a second data line;
a first pass gate comprising:
a first terminal of the first pass gate being coupled to the first bit line;
a second terminal of the first pass gate being coupled to the first data line;
a third terminal of the first pass gate being configured to receive a first control signal; and
a fourth terminal of the first pass gate being configured to receive a second control signal, the second control signal being inverted from the first control signal; and
a second pass gate comprising:
a first terminal of the second pass gate being coupled to the first bit line bar;
a second terminal of the second pass gate being coupled to the second data line;
a third terminal of the second pass gate being configured to receive at least the first control signal or a third control signal; and
a fourth terminal of the second pass gate being configured to receive at least the second control signal or a fourth control signal, the fourth control signal being inverted from the third control signal.

### Claim 11

A memory array comprising:
a three-dimensional array comprising:
a first set of memory cells arranged in a first column; and
a second set of memory cells arranged in a second column;
the first column comprising:
a first bit line;
a first bit line bar; and
a first word line;
the second column comprising:
the first bit line bar;
a second bit line; and
a second word line;
a first pre-charge circuit coupled to the first bit line;
a second pre-charge circuit coupled to the first bit line bar; and
a set of switching elements,
wherein the first column and the second column are configured to share the first bit line bar;
at least two of the first bit line, the first bit line bar or the second bit line are in a first plane; and
the first word line and the second word line are in a second plane, the second plane intersecting the first plane.

### Claim 12 (depends on 11)

The memory array of claim 11, further comprising:
a set of data lines; and
a sense amplifier coupled to the set of switching elements by the set of data lines.

### Claim 13 (depends on 12)

The memory array of claim 12, wherein the set of switching elements comprises:
a first switching element having a first terminal coupled to the first bit line;
a second switching element having a first terminal coupled to the first bit line;
a third switching element having a first terminal coupled to the first bit line bar; and
a fourth switching element having a first terminal coupled to the second bit line.

### Claim 14 (depends on 13)

The memory array of claim 13, wherein the set of data lines comprises:
a first data line coupled between a first terminal of the sense amplifier and a second terminal of the second switching element;
a second data line coupled between a second terminal of the sense amplifier and a second terminal of the third switching element; and
a third data line coupled between the first terminal of the sense amplifier and a second terminal of the fourth switching element.

### Claim 15 (depends on 11)

The memory array of claim 11, wherein the first pre-charge circuit comprises:
a first p-type transistor comprising:
a first terminal of the first p-type transistor;
a second terminal of the first p-type transistor being coupled to the first bit line; and
a third terminal of the first p-type transistor being coupled to a first supply voltage; and
the second pre-charge circuit comprises:
a second p-type transistor comprising:
a first terminal of the second p-type transistor being coupled to at least the first terminal of the first p-type transistor;
a second terminal of the second p-type transistor being coupled to the first bit line bar; and
a third terminal of the second p-type transistor being coupled to the first supply voltage.

### Claim 16 (depends on 15)

The memory array of claim 15, wherein the second pre-charge circuit further comprises:
a third p-type transistor comprising:
a first terminal of the third p-type transistor being coupled to the first terminal of the first p-type transistor and the first terminal of the second p-type transistor;
a second terminal of the third p-type transistor being coupled to the second bit line; and
a third terminal of the third p-type transistor being coupled to the first supply voltage.

### Claim 17 (depends on 11)

The memory array of claim 11, wherein the second plane is substantially orthogonal to the first plane.

### Claim 18

A method comprising:
forming a first column of memory cells, the first column of memory cells comprising:
a first bit line;
a first word line; and
a first bit line bar, the first bit line and the first bit line bar being in a first plane;
forming a second column of memory cells, the second column of memory cells comprising:
the first bit line bar;
a second word line, the first word line and the second word line being in a second plane intersecting the first plane, the first column of memory cells and the second column of memory cells being a three-dimensional array; and
a second bit line;
sharing the first bit line bar between the first column of memory cells and the second column of memory cells;
sharing a first pre-charge circuit between the first column of memory cells and the second column of memory cells, the first pre-charge circuit being coupled to at least the first bit line bar; and
providing a word line driver to the first word line and the second word line, the word line driver being below the three-dimensional array.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
providing a local input output circuit to the first bit line, the first bit line bar or the second bit line.

### Claim 20 (depends on 19)

The method of claim 19, wherein providing the local input output circuit to the first bit line, the first bit line bar or the second bit line comprises:
coupling a set of data lines to the first bit line, the first bit line bar or the second bit line by a set of bit line switching elements.