# US 10,121,452 B2 · Display device having compensating capacitors for different wiring lengths and method of manufacturing the same

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- Number: US 10,121,452 B2
- Document ID: US10121452B2
- Status: Granted
- Kind: B2
- Application number: 15/346,046
- Filed: 2016-11-08
- Published: 2017-06-01
- Granted: 2018-11-06
- Earliest claimed: 2015-11-26
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Byongwook Shin; Jaeho Sim; Jungyoup Suk
- Web page: https://patentgrep.com/patent/US10121452B2

## CPC

- G09G 5/10: Intensity circuits
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- H10D 86/021: {of multiple TFTs}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0278: Details of driving circuits arranged to drive both scan and data electrodes
- G09G 2310/0281: Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
- G09G 2320/0209: Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- H10K 59/1201: {Manufacture or treatment}
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

Provided are a display device and a method of manufacturing the same. A display device comprises a display area, a non-display area, signal lines, and compensating capacitors. The display area and the non-display area are defined on a substrate. The signal lines are located within the display area, and their wiring lengths differ depending on location. The compensating capacitors are connected to at least one of the signal lines.

## Claims

### Claim 1

A display device comprising:
a display area and non-display area defined on a substrate;
signal lines whose wiring length differs depending on location, which are located within the display area; and
compensating capacitors each connected to at least one of the signal lines,
wherein adjacent N signal lines (N is an integer greater than or equal to 2) are combined into one group, and the compensating capacitor corresponding to the group converges to a single capacitance value.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the compensating capacitors have a different capacitance value depending on the length of the signal lines.

### Claim 3 (depends on 1)

The display device of claim 1, wherein the compensating capacitors are formed so that parasitic capacitors existing between the signal lines have a capacitance value, with variation ranging from 1 to 20%.

### Claim 4 (depends on 1)

The display device of claim 1, wherein the compensating capacitors are arranged in non-display areas provided on the upper and lower sides of the display area.

### Claim 5 (depends on 1)

The display device of claim 1, wherein the compensating capacitors are arranged in non-display areas provided on the left and right sides of the display area.

### Claim 6 (depends on 1)

The display device of claim 1, wherein the compensating capacitors are arranged in non-display areas provided on the upper, lower, left, and right sides of the display area.

### Claim 7 (depends on 1)

The display device of claim 1, wherein one end of the compensating capacitors is connected to at least one of the signal lines, and the other end is electrically floating or connected to a power source.

### Claim 8 (depends on 1)

The display device of any one of claim 1, wherein the display panel has a curved shape.

### Claim 9 (depends on 1)

The display device of any one of claim 1, wherein the display panel has a circular shape.

### Claim 10 (depends on 1)

The display device of any one of claim 1, wherein the display panel has an elliptical shape.

### Claim 11

A method for manufacturing a display device, the method comprising:
defining a display area and a non-display area on a substrate;
arranging signal lines whose wiring length differs depending on location, within the display area; and
forming compensating capacitors in such a manner that each compensating capacitor is connected to at least one of the signal lines,
wherein adjacent N signal lines (N is an integer greater than or equal to 2) are combined into one group, and the compensating capacitor corresponding to the group converges to a single capacitance value.

### Claim 12 (depends on 11)

The method of claim 11, wherein, in the forming of compensating capacitors, the compensating capacitors have a different capacitance value depending on the length of the signal lines.
