# US 10,121,448 B2 · Semiconductor device, and display device and electronic device utilizing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,448 B2 - Document ID: US10121448B2 - Status: Granted - Kind: B2 - Application number: 15/880,590 - Filed: 2018-01-26 - Published: 2018-08-16 - Granted: 2018-11-06 - Earliest claimed: 2002-12-25 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Hajime Kimura; Yutaka Shionoiri - Web page: https://patentgrep.com/patent/US10121448B2 ## CPC - G09G 5/003: {Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092)} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/36: using liquid crystals - H03K 19/018507: {Interface arrangements} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2330/021: Power management, e.g. power saving - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased. ## Claims ### Claim 1 A display device comprising: pixels; the gate line driver circuit; and a signal line driver circuit; wherein the pixels and the gate line driver circuit are provided over a substrate, wherein at least part of the signal line driver circuit is provided with an IC chip, wherein the IC chip comprises a single crystal substrate or an SOI substrate, wherein the gate line driver circuit is electrically connected to the pixels, wherein the signal line driver circuit is electrically connected to the pixels, wherein the gate line driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, and wherein: one of a source and a drain of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; one of a source and a drain of the second transistor is electrically connected to a third wiring; the other of the source and the drain of the second transistor is electrically connected to the second wiring; a gate of the second transistor is electrically connected to a fourth wiring; one of a source and a drain of the third transistor is electrically connected to a fifth wiring; the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to the fifth wiring; one of a source and a drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fourth transistor; one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor; and a gate of the fifth transistor is electrically connected to the fourth wiring. ### Claim 2 (depends on 1) The display device according to claim 1, wherein the IC chip is connected to the substrate by COG. ### Claim 3 (depends on 1) The display device according to claim 1, wherein the IC chip is connected to the substrate by TAB. ### Claim 4 (depends on 1) The display device according to claim 1; the one of the source and the drain of the first transistor is directly connected to the first wiring; the other of the source and the drain of the first transistor is directly connected to the second wiring; the one of the source and the drain of the second transistor is directly connected to the third wiring; the other of the source and the drain of the second transistor is directly connected to the second wiring; the gate of the second transistor is directly connected to the fourth wiring; the one of the source and the drain of the third transistor is directly connected to the fifth wiring; the gate of the third transistor is directly connected to the fifth wiring; the one of the source and the drain of the fourth transistor is directly connected to the third wiring; the other of the source and the drain of the fourth transistor is directly connected to the fourth transistor; the one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor; and the gate of the fifth transistor is directly connected to the fourth wiring. ### Claim 5 (depends on 1) The display device according to claim 1; wherein the gate line driver circuit further comprises a sixth transistor and a seventh transistor, and wherein: a gate of the sixth transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a sixth wiring; a gate of the seventh transistor is electrically connected to the fourth wiring; and one of a source and a drain of the seventh transistor is electrically connected to the sixth wiring. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein: the one of the source and the drain of the first transistor is directly connected to a first wiring; the other of the source and the drain of the first transistor is directly connected to a second wiring; the one of the source and the drain of the second transistor is directly connected to a third wiring; the other of the source and the drain of the second transistor is directly connected to the second wiring; the gate of the second transistor is directly connected to a fourth wiring; the one of the source and the drain of the third transistor is directly connected to the fifth wiring; the gate of the third transistor is directly connected to the fifth wiring; the one of the source and the drain of the fourth transistor is directly connected to the third wiring; the other of the source and the drain of the fourth transistor is directly connected to the fourth transistor; the one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor; the gate of the fifth transistor is directly connected to the fourth wiring; the gate of the sixth transistor is directly connected to the gate of the first transistor; the one of the source and the drain of the sixth transistor is directly connected to a sixth wiring; the gate of the seventh transistor is directly connected to the fourth wiring; and the one of the source and the drain of the seventh transistor is directly connected to the sixth wiring. ### Claim 7 A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; and a fifth transistor; wherein: one of a source and a drain of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; one of a source and a drain of the second transistor is electrically connected to a third wiring; the other of the source and the drain of the second transistor is electrically connected to the second wiring; a gate of the second transistor is electrically connected to a fourth wiring; one of a source and a drain of the third transistor is electrically connected to a fifth wiring; the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor; a gate of the third transistor is electrically connected to the fifth wiring; one of a source and a drain of the fourth transistor is electrically connected to the third wiring; the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fourth transistor; one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor; and a gate of the fifth transistor is electrically connected to the fourth wiring. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein: the one of the source and the drain of the first transistor is directly connected to the first wiring; the other of the source and the drain of the first transistor is directly connected to the second wiring; the one of the source and the drain of the second transistor is directly connected to the third wiring; the other of the source and the drain of the second transistor is directly connected to the second wiring; the gate of the second transistor is directly connected to the fourth wiring; the one of the source and the drain of the third transistor is directly connected to the fifth wiring; the gate of the third transistor is directly connected to the fifth wiring; the one of the source and the drain of the fourth transistor is directly connected to the third wiring; the other of the source and the drain of the fourth transistor is directly connected to the fourth transistor; the one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor; and the gate of the fifth transistor is directly connected to the fourth wiring. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, further comprising a sixth transistor and a seventh transistor, wherein: a gate of the sixth transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a sixth wiring; a gate of the seventh transistor is electrically connected to the fourth wiring; and one of a source and a drain of the seventh transistor is electrically connected to the sixth wiring. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein: the one of the source and the drain of the first transistor is directly connected to the first wiring; the other of the source and the drain of the first transistor is directly connected to the second wiring; the one of the source and the drain of the second transistor is directly connected to the third wiring; the other of the source and the drain of the second transistor is directly connected to the second wiring; the gate of the second transistor is directly connected to the fourth wiring; the one of the source and the drain of the third transistor is directly connected to the fifth wiring; the gate of the third transistor is directly connected to the fifth wiring; the one of the source and the drain of the fourth transistor is directly connected to the third wiring; the other of the source and the drain of the fourth transistor is directly connected to the fourth transistor; the one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor; the gate of the fifth transistor is directly connected to the fourth wiring; the gate of the sixth transistor is directly connected to the gate of the first transistor; the one of the source and the drain of the sixth transistor is directly connected to the sixth wiring; the gate of the seventh transistor is directly connected to the fourth wiring; and the one of the source and the drain of the seventh transistor is directly connected to the sixth wiring.