# US 10,121,443 B2 · Display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,443 B2 - Document ID: US10121443B2 - Status: Granted - Kind: B2 - Application number: 15/430,569 - Filed: 2017-02-13 - Published: 2018-08-16 - Granted: 2018-11-06 - Earliest claimed: 2017-02-13 - Assignees: Innolux Corporation - Applicants: Innolux Corporation - Inventors: Shinji Konoshita - Web page: https://patentgrep.com/patent/US10121443B2 ## CPC - G09G 3/3677: {suitable for active matrices only} - G09G 3/3614: {Control of polarity reversal in general} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display panel includes a first gate driving circuit, a second gate driving circuit, a first pixel element and a second pixel element. The first gate driving circuit generates a first gate pulse signal. The second gate driving circuit generates a second gate pulse signal. The first gate pulse signal and the second gate pulse signal are simultaneously activated. The first pixel element receives the first gate pulse signal. The second pixel element receives the second gate pulse signal. While the first pixel element is in a negative polarity state, the second pixel element is in a positive polarity state, the first pixel element is turned off in response to a first low gate voltage of the first gate pulse signal, and the second pixel element is turned off in response to a second low gate voltage of the second gate pulse signal. ## Claims ### Claim 1 A display panel, comprising: a first gate driving circuit generating a first gate pulse signal; a second gate driving circuit generating a second gate pulse signal, wherein the first gate pulse signal and the second gate pulse signal are simultaneously activated; and a first pixel element row comprising a first pixel element arid a second pixel element, wherein the first pixel element receives the first gate pulse signal, and the second pixel element receives the second gate pulse signal, wherein while the first pixel element is in a negative polarity state, the second pixel element is in a positive polarity state, the first pixel element is turned off in response to a first low gate voltage of the first gate pulse signal, and the second pixel element is turned off in response to a second low gate voltage of the second gate pulse signal, wherein while the first pixel element is in the positive polarity state, the second pixel element is in the negative polarity state, the first pixel element is turned off in response to a second low gate voltage of the first gate pulse signal, and the second pixel element is turned off in response to a first low gate voltage of the second gate pulse signal, wherein the first low gate voltage of the first gate pulse signal is less than the second low gate voltage of the first gate pulse signal, and the first low gate voltage of the second gate pulse signal is less than the second low gate voltage of the second gate pulse signal. ### Claim 2 (depends on 1) The display panel as claimed in claim 1, wherein the first gate driving circuit comprises a first gate driver that receives a first clock signal, a second clock signal and a first previous gate pulse signal, and the first gate driver generates the first gate pulse signal, wherein the second gate driving circuit comprises a second gate driver that receives the first clock signal, the second clock signal and a second previous gate pulse signal, and the second gate driver generates the second gate pulse signal. ### Claim 3 (depends on 2) The display panel claimed in claim 2, wherein the first gate driver comprises: a latch circuit receiving the first clock signal and the first previous gate pulse signal, wherein the latch circuit is in a set state or a reset state according to the first clock signal and the first previous gate pulse signal; and an output circuit receiving the second clock signal and generating the first gate pulse signal, wherein the first gate pulse signal from the output circuit includes the second clock signal when the latch circuit is in the set state, and the first gate pulse signal from the output circuit includes the first low gate voltage or the second low gate voltage when the latch circuit is in the reset state. ### Claim 4 (depends on 2) The display panel as claimed in claim 2, wherein the first gate driving circuit further comprises a third gate driver that receives the first clock signal and generates a third gate pulse signal, wherein the second gate driving circuit further comprises a fourth gate driver that receives the first clock signal and generates a fourth gate pulse signal. ### Claim 5 (depends on 4) The display panel as claimed in claim 4, wherein the first pixel element receives the first gate pulse signal and a first video signal from a source bus, and the second pixel element receives the second gate pulse signal and a second video signal from the source bus. ### Claim 6 (depends on 5) The display panel as claimed in claim 5, wherein the display panel further comprises a second pixel element row with a third pixel element and a fourth pixel element, wherein the third pixel element receives the third gate pulse signal and the first video signal from the source bus, and the fourth pixel element receives the fourth gate pulse signal and the second video signal from the source bus. ### Claim 7 (depends on 5) The display panel as claimed in claim 5, wherein the display panel further comprises a second pixel element row with a third pixel element and a fourth pixel element, wherein the third pixel element receives the third gate pulse signal and the second video signal from the source bus, and the fourth pixel element receives the fourth gate pulse signal and a third video signal from the source bus. ### Claim 8 (depends on 5) The display panel as claimed in claim 5, wherein the display panel further comprises a second pixel element row with a third pixel element and a fourth pixel element, wherein the third pixel element receives the fourth gate pulse signal and the first video signal from the source bus, and the fourth pixel element receives the third gate pulse signal and the second video signal from the source bus. ### Claim 9 A display panel, comprising: a first gate driving circuit generating a first gate pulse signal; a second gate driving circuit generating a second gate pulse signal; a first pixel element row receiving the first gate pulse signal; and a second pixel element row receiving the second gate pulse signal, wherein while plural pixel elements of the first pixel element row are in a negative polarity state, plural pixel elements of the second pixel element row are in a positive polarity state, the plural pixel elements of the first pixel element row are turned off in response to a first low gate voltage of the first gate pulse signal, and the plural pixel elements of the second pixel element row are turned off in response to a second low gate voltage of the second gate pulse signal, wherein while the plural pixel elements of the first pixel element row are in the positive polarity state, the plural pixel elements of the second pixel element row are in the negative polarity state, the plural pixel elements of the first pixel element row are turned off in response to a second low gate voltage of the first gate pulse signal, and the plural pixel elements of the second pixel element row are turned off in response to a first low gate voltage of the second gate pulse signal, wherein the first low gate voltage of the first gate pulse signal is less than the second low gate voltage of the first gate pulse signal, and the first low gate voltage of the second gate pulse signal is less than the second low gate voltage of the second gate pulse signal. ### Claim 10 (depends on 9) The display panel as claimed in claim 9, wherein the first gate driving circuit comprises a first gate driver that receives a first clock signal, a second clock signal and a first previous gate pulse signal, and the first gate driver generates the first gate pulse signal, wherein the second gate driving circuit comprises a second gate driver that receives the first clock signal, the second clock signal and a second previous gate pulse signal, and the second gate driver generates the second gate pulse signal. ### Claim 11 (depends on 10) The LCD panel as claimed in claim 10, wherein the first gate driver comprises: a latch circuit receiving the first clock signal and the first previous gate pulse signal, wherein the latch circuit is in a set state or a reset state according to the first clock signal and the first previous gate pulse signal; and an output circuit receiving the second clock signal and generating the first gate pulse signal, wherein the first gate pulse signal from the output circuit contains the second pulse signal when the latch circuit is in the set state, and the first gate pulse signal from the output circuit contains the first low gate voltage or the second low gate voltage when the latch circuit is in the reset state. ### Claim 12 A display device, comprising: a driving control unit; and a display panel electrically connected to the driving control unit, wherein the display panel comprises: a first gate driving circuit generating a first gate pulse signal; a second gate driving circuit generating a second gate pulse signal; wherein the first gate pulse signal and the second gate pulse signal are simultaneously activated; and a first pixel element row comprising a first pixel element and a second pixel element, wherein the first pixel element receives the first gate pulse signal, and the second pixel element receives the second gate pulse signal, wherein while the first pixel element is in a negative polarity state, the second pixel element is in a positive polarity state, the first pixel element is turned off in response to a first low gate voltage of the first gate pulse signal, and the second pixel element is turned off in response to a second low gate voltage of the second gate pulse signal, wherein while the first pixel element is in the positive polarity state, the second pixel element is in the negative polarity state, the first pixel element is turned off in response to a second low gate voltage of the first gate pulse signal, and the second pixel element is turned off in response to a first low gate voltage of the second gate pulse signal, wherein the first low gate voltage of the first gate pulse signal is less than the second low gate voltage of the first gate pulse signal, and the first low gate voltage of the second gate pulse signal is less than the second low gate voltage of the second gate pulse signal. ### Claim 13 (depends on 12) The display device as claimed in claim 12, wherein the first gate driving circuit comprises a first gate driver that receives a first clock signal, a second clock signal and a first previous gate pulse signal, and the first gate driver generates the first gate pulse signal, wherein the second gate driving circuit comprises a second gate driver that receives the first clock signal, the second clock signal and a second previous gate pulse signal, and the second gate driver generates the second gate pulse signal. ### Claim 14 (depends on 13) The display device as claimed in claim 13, wherein the first gate driver comprises: a latch circuit receiving the first clock signal and the first previous gate pulse signal, wherein the latch circuit is in a set state or a reset state according to the first clock signal and the first previous gate pulse signal; and an output circuit receiving the second clock signal, the first low gate voltage and the second low gate voltage, and generating the first gate pulse signal, wherein the first gate pulse signal from the output circuit includes the second clock signal when the latch circuit is in the set state, and the first gate pulse signal from the output circuit includes the first low gate voltage of the first gate pulse signal or the second low gate voltage of the first gate pulse signal when the latch circuit is in the reset state. ### Claim 15 (depends on 13) The display device as claimed in claim 13, wherein the first gate driving circuit further comprises a third gate driver that receives the first clock signal and generates a third gate pulse signal, wherein the second gate driving circuit further comprises a fourth gate driver that receives the first clock signal, the second clock signal and the second gate pulse signal, and the fourth gate driver generates a fourth gate pulse signal. ### Claim 16 (depends on 15) The display device as claimed in claim 15, wherein the first pixel element receives the first gate pulse signal and a first video signal from a source bus, and the second pixel element receives the second gate pulse signal and a second video signal from the source bus. ### Claim 17 (depends on 16) The display device as claimed in claim 16, wherein the display panel further comprises a second pixel element row with a third pixel element and a fourth pixel element, wherein the third pixel element receives the third gate pulse signal and the first video signal from the source bus, and the fourth pixel element receives the fourth gate pulse signal and the second video signal from the source bus. ### Claim 18 (depends on 16) The display device as claimed in claim 16, wherein the display panel further comprises a second pixel element row with a third pixel element and a fourth pixel element, wherein the third pixel element receives the third gate pulse signal and the second video signal from the source bus, and the fourth pixel element receives the fourth gate pulse signal and a third video signal from the source bus. ### Claim 19 (depends on 16) The display device as claimed in claim 16, wherein the display panel further comprises a second pixel element row with a third pixel element and a fourth pixel element, wherein the third pixel element receives the fourth gate pulse signal and the first video signal from the source bus, and the fourth pixel element receives the third gate pulse signal and the second video signal from the source bus. ### Claim 20 (depends on 12) The display device as claimed in claim 12, wherein driving control unit comprises: a clock generator generating the first clock signal and the second clock signal; a low gate voltage generator generating the first low gate voltage of the first gate pulse signal, the first low gate voltage of the second gate pulse signal, the second low gate voltage of the first gate pulse signal, and the second low gate voltage of the second gate pulse signal; a source driver generating the first video signal and the second video signal; and a timing controller generating a enable pulse signal.