# US 10,121,442 B2 · Driving methods and driving devices of gate driver on array (GOA) circuit

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- Number: US 10,121,442 B2
- Document ID: US10121442B2
- Status: Granted
- Kind: B2
- Application number: 15/328,629
- Filed: 2017-01-17
- Published: 2018-07-26
- Granted: 2018-11-06
- Earliest claimed: 2017-01-17
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Longqiang Shi; Shu Jhih Chen
- Web page: https://patentgrep.com/patent/US10121442B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2310/06: Details of flat display driving waveforms
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G11C 19/182: {in combination with semiconductor elements, e.g. bipolar transistors, diodes}
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure relates to a driving method and a driving unit of GOA circuits. The driving unit includes a timing control chip and a GOA circuit including a plurality of cascaded GOA driving units. The timing control chip inputs first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level. The first clock signals and the second clock signals are two different clock signals selected from one clock signals set including eight high-frequency clock signals (CK1˜CK8), wherein CKm and CKm+4 are inverting signals. A period of each of the high-frequency clock signals is T, and a high-potential pulse width within the period (T) is T1 During a scanning driving process of each of frames, the high-potential pulse width of the high-frequency clock signals (CKm) is T1m, T1m<T1, m=1, 2, 3, and 4.

## Claims

### Claim 1

A driving method of GOA circuits, the GOA circuits comprises a plurality of cascaded-connected GOA driving units, and the driving method comprising:
inputting first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level; and
wherein the first clock signals and the second clock signals are two different clock signals selected from one clock signals set comprising eight high-frequency clock signals (CK1˜CK8), wherein CKm and CKm+4 are inverting signals, and m=1, 2, 3, 4;
the first clock signals start from the CK5 to output the high-frequency clock signals cyclically, and the second clock signals starts from the CK1 to output the high-frequency clock signals (CK1˜CK8) cyclically, wherein a period of each of the high-frequency clock signals is T, and a high-potential pulse width within the period (T) is T1; and
during a scanning driving process of each of frames, the high-potential pulse width of the high-frequency clock signals (CKm) is T1m, T1m<T1, m=1, 2, 3, and 4.

### Claim 2 (depends on 1)

The driving method as claimed in claim 1, wherein ½T1≤T1m<T1.

### Claim 3 (depends on 1)

The driving method as claimed in claim 1, wherein T11=T12=T13=T14=½T1.

### Claim 4 (depends on 3)

The driving method as claimed in claim 3, wherein a first period of the high-frequency clock signals (CK1) is delayed by a time period (H) of the scanning initial signals, wherein T=8H, T1=3.2H.

### Claim 5 (depends on 4)

The driving method as claimed in claim 4, wherein the GOA driving units at each of the levels comprises:
a pull-up control circuit, a pull-up circuit, a level transfer circuit, a boast capacitor, and a pull-down holding circuit,
the pull-up control circuit outputs gate control signals of the current level in accordance with the second clock signals and the transfer signals (STn−4), the pull-up circuit outputs the scanning driving signals of the current level in accordance with the first clock signals and the gate control signals of the current level, the pull-down holding circuit is configured for pulling down the gate control signals of the current level and the scanning driving signal of the current level to be at a low potential during a non-driving period of the GOA driving unit of the current level.

### Claim 6 (depends on 5)

The driving method as claimed in claim 5, wherein the pull-up control circuit comprises a first pull-up transistor and a second pull-up transistor, the first pull-up transistor and the second pull-up transistor are connected to each other to receive the second clock signals, a source of the first pull-up transistor receives the corresponding transfer signals (STn−4), a drain of the first pull-up transistor connects to a source of the second pull-up transistor, a drain of the second pull-up transistor operates as an output end of the pull-up control circuit to output the gate control signals of the current level.

### Claim 7 (depends on 5)

The driving method as claimed in claim 5, wherein the pull-up circuit comprises a fourth pull-up transistor, a gate of the fourth pull-up transistor connects to the output end of the pull-up control circuit to receive the gate control signals, a source of the fourth pull-up transistor receives the first clock signals, a drain of the fourth pull-up transistor operates as the output end of the pull-up circuit to output the scanning driving signal of the current level.

### Claim 8 (depends on 5)

The driving method as claimed in claim 5, wherein the level transfer circuit comprises a transfer transistor, a gate of the transfer transistor connects to the output end of the pull-up control circuit to receive the gate control signals, a source of the transfer transistor connects to the first clock signals, and a drain of the transfer transistor operates as the output end of the level transfer circuit to output the scanning driving signals at the current level.

### Claim 9 (depends on 5)

The driving method as claimed in claim 5, wherein the pull-down holding circuit comprises a first pull-down holding circuit and a second pull-down holding circuit for pulling down the gate control signals and the scanning driving signals to be at the low potential in an alternated manner;
the first pull-down holding circuit and the second pull-down holding circuit have the same circuit structure, the first pull-down holding circuit and the second pull-down holding circuit respectively includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, drains of the first transistor, the second transistor, and the third transistor connect to the constant-voltage potential, gates of the first transistor, the second transistor, and the third transistor are interconnected to receive control signals, sources of the first transistor connects to the scanning driving signal;
a source of the second transistor connect to the transfer signals, a source of the third transistor connects to the gate control signals, a gate and a source of the fourth transistor are connected to receive pull-down clock signals, a drain of the fourth transistor connects to a source of the fifth transistor, a gate of the fifth transistor connects to the gate control signals, a drain of the fifth transistor connects to the constant-voltage potential;
a source of the sixth transistor connects to the source of the fourth transistor to receive the pull-down clock signals, a gate of the sixth transistor connects to the drain of the fourth transistor, a drain of the sixth transistor connects to a source of the seventh transistor; a gate of the seventh transistor connects to the gate control signals, and a drain of the seventh transistor connects to the constant-voltage potential, wherein the drain of the sixth transistor outputs the control signals to connect to the gates of the first transistor, the second transistor, and the third transistor;
wherein the first pull-down clock signals received by the first pull-down holding circuit and the second pull-down clock signals are low frequency signals, and a high potential and the low potential of the first pull-down clock signals are respectively logically inverted from the high potential and the low potential of the second pull-down clock signals.

### Claim 10 (depends on 5)

The driving method as claimed in claim 5, wherein one end of the boast capacitor connects to the output end of the pull-up control circuit, and the other end of the boast capacitor connects to the output end of the pull-up circuit.

### Claim 11

A driving unit of GOA circuits, comprising:
a timing control chip and a GOA circuit comprising a plurality of cascaded GOA driving units, the timing control chip inputs first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level; and
wherein the first clock signals and the second clock signals are two different clock signals selected from one clock signals set comprising eight high-frequency clock signals (CK1˜CK8), wherein CKm and CKm+4 are inverting signals, and m=1, 2, 3, 4;
the first clock signals start from the CK5 to output the high-frequency clock signals cyclically, and the second clock signals starts from the CK1 to output the high-frequency clock signals (CK1˜CK8) cyclically, wherein a period of each of the high-frequency clock signals is T, and a high-potential pulse width within the period (T) is T1; and
during a scanning driving process of each of frames, the high-potential pulse width of the high-frequency clock signals (CKm) is T1m, T1m<T1, m=1, 2, 3, and 4.

### Claim 12 (depends on 11)

The driving unit as claimed in claim 11, wherein 2 T1<T1m<T1.

### Claim 13 (depends on 11)

The driving unit as claimed in claim 11, wherein T11=T12=T13=T14=1 2 T1.

### Claim 14 (depends on 13)

The driving unit as claimed in claim 13, wherein a first period of the high-frequency clock signals (CK1) is delayed by a time period (H) of the scanning initial signals, wherein T=8H, T1=3.2H.

### Claim 15 (depends on 14)

The driving unit as claimed in claim 14, wherein the GOA driving units at each of the levels comprises:
a pull-up control circuit, a pull-up circuit, a level transfer circuit, a boast capacitor, and a pull-down holding circuit,
the pull-up control circuit outputs gate control signals of the current level in accordance with the second clock signals and the transfer signals (STn−4), the pull-up circuit outputs the scanning driving signals of the current level in accordance with the first clock signals and the gate control signals of the current level, the pull-down holding circuit is configured for pulling down the gate control signals of the current level and the scanning driving signal of the current level to be at a low potential during a non-driving period of the GOA driving unit of the current level.

### Claim 16 (depends on 15)

The driving unit as claimed in claim 15, wherein the pull-up control circuit comprises a first pull-up transistor and a second pull-up transistor, the first pull-up transistor and the second pull-up transistor are connected to each other to receive the second clock signals, a source of the first pull-up transistor receives the corresponding transfer signals (STn−4), a drain of the first pull-up transistor connects to a source of the second pull-up transistor, a drain of the second pull-up transistor operates as an output end of the pull-up control circuit to output the gate control signals of the current level.

### Claim 17 (depends on 15)

The driving unit as claimed in claim 15, wherein the pull-up circuit comprises a fourth pull-up transistor, a gate of the fourth pull-up transistor connects to the output end of the pull-up control circuit to receive the gate control signals, a source of the fourth pull-up transistor receives the first clock signals, a drain of the fourth pull-up transistor operates as the output end of the pull-up circuit to output the scanning driving signal of the current level.

### Claim 18 (depends on 15)

The driving unit as claimed in claim 15, wherein the level transfer circuit comprises a transfer transistor, a gate of the transfer transistor connects to the output end of the pull-up control circuit to receive the gate control signals, a source of the transfer transistor connects to the first clock signals, and a drain of the transfer transistor operates as the output end of the level transfer circuit to output the scanning driving signals at the current level.

### Claim 19 (depends on 15)

The driving unit as claimed in claim 15, wherein the pull-down holding circuit comprises a first pull-down holding circuit and a second pull-down holding circuit for pulling down the gate control signals and the scanning driving signals to be at the low potential in an alternated manner;
the first pull-down holding circuit and the second pull-down holding circuit have the same circuit structure, the first pull-down holding circuit and the second pull-down holding circuit respectively includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, drains of the first transistor, the second transistor, and the third transistor connect to the constant-voltage potential, gates of the first transistor, the second transistor, and the third transistor are interconnected to receive control signals, sources of the first transistor connects to the scanning driving signal;
a source of the second transistor connect to the transfer signals, a source of the third transistor connects to the gate control signals, a gate and a source of the fourth transistor are connected to receive pull-down clock signals, a drain of the fourth transistor connects to a source of the fifth transistor, a gate of the fifth transistor connects to the gate control signals, a drain of the fifth transistor connects to the constant-voltage potential;
a source of the sixth transistor connects to the source of the fourth transistor to receive the pull-down clock signals, a gate of the sixth transistor connects to the drain of the fourth transistor, a drain of the sixth transistor connects to a source of the seventh transistor; a gate of the seventh transistor connects to the gate control signals, and a drain of the seventh transistor connects to the constant-voltage potential, wherein the drain of the sixth transistor outputs the control signals to connect to the gates of the first transistor, the second transistor, and the third transistor;
wherein the first pull-down clock signals received by the first pull-down holding circuit and the second pull-down clock signals are low frequency signals, and a high potential and the low potential of the first pull-down clock signals are respectively logically inverted from the high potential and the low potential of the second pull-down clock signals.

### Claim 20 (depends on 15)

The driving unit as claimed in claim 15, wherein one end of the boast capacitor connects to the output end of the pull-up control circuit, and the other end of the boast capacitor connects to the output end of the pull-up circuit.