# US 10,121,438 B2 · Shift register and display device

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- Number: US 10,121,438 B2
- Document ID: US10121438B2
- Status: Granted
- Kind: B2
- Application number: 15/197,786
- Filed: 2016-06-30
- Published: 2017-01-19
- Granted: 2018-11-06
- Earliest claimed: 2015-07-16
- Assignees: HannStar Display (Nanjing) Corporation; Hannstar Display Corp.
- Applicants: HannStar Display (Nanjing) Corporation; HannStar Display Corporation
- Inventors: Tean-Sen Jen; Sung-Chun Lin; Hsuan-Chen Liu; Chien-Ting Chan
- Web page: https://patentgrep.com/patent/US10121438B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G09G 3/3696: {Generation of voltages supplied to electrode drivers}
- G11C 19/287: {Organisation of a multiplicity of shift registers}
- G09G 2230/00: Details of flat display driving waveforms
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology
- G09G 2300/0809: Several active elements per pixel in active matrix panels
- G09G 2310/0248: Precharge or discharge of column electrodes before or after applying exact column voltages
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A shift register and a display device are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives the pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal and first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The period of the first second pull-down control signal and the period of the second pull-down control signal are in a range from 12 frames to 180 frames.

## Claims

### Claim 1

A shift register, comprising:
a pre-charge unit configured to receive a first input signal and a second input signal and output a pre-charge signal via a first node based on the first input signal and the second input signal;
a pull-up unit that is coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal and output a scan signal via a second node based on the pre-charge signal and the clock signal;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and control whether to pull down the scan signal to a reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and control whether to keep the scan signal at the reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
wherein periods of the first pull-down control signal and the second pull-down control signal are in a range from 12 frames to 180 frames, and a time interval between a rising edge of the first pull-down control signal and a falling edge of the second pull-down control signal is in a range from 2 microseconds to 4 microseconds.

### Claim 2 (depends on 1)

The shift register of claim 1, wherein the period of the first pull-down control signal is substantially the same as the period of the second pull-down control signal, and the period of the first pull-down control signal and the period of the second pull-down control signal are 120 frames.

### Claim 3 (depends on 1)

The shift register of claim 1, wherein the pre-charge unit comprises:
a first transistor, wherein a gate of the first transistor is configured to receive a starting signal, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and
a second transistor, wherein a gate and a first source/drain of the second transistor are configured to receive another scan signal outputted by a next two stage of shift register to the shift register, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor.

### Claim 4 (depends on 1)

The shift register of claim 1, wherein the pre-charge unit comprises:
a first transistor, wherein a gate of the first transistor is configured to receive another scan signal outputted by a previous two stage of shift register to the shift register, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and
a second transistor, wherein a gate of the second transistor is configured to receive another scan signal outputted by a next two stage of shift register to the shift register, a first source/drain of the second transistor is configured to receive a backward input signal, and a second source/drain of the second transistor is coupled to the second source/ drain of the first transistor.

### Claim 5 (depends on 1)

The shift register of claim 1, wherein the pull-up unit comprises:
a third transistor, wherein a gate of the third transistor is configured to receive the pre-charge signal, a first source/drain of the third transistor is configured to receive the clock signal, and a second source/drain of the third transistor is configured to output the scan signal; and
a capacitor, wherein a first terminal of the capacitor is coupled to the gate of the third terminal, and a second terminal of the capacitor is coupled to the second source/drain of the third transistor.

### Claim 6 (depends on 1)

The shift register of claim 1, wherein the first pull-down unit comprises:
a fourth transistor, wherein a gate and a first source/drain of the fourth transistor are configured to input the first pull-down control signal;
a fifth transistor, wherein a gate of the fifth transistor is configured to input the second pull-down control signal, a first source/drain of the fifth transistor is configured to input the reference voltage level, and a second source/drain of the fifth transistor is coupled to the second source/drain of the fourth transistor;
a sixth transistor, wherein a gate of the sixth transistor is coupled to the first node, a first source/drain of the sixth transistor is configured to input the reference voltage level, and a second source/drain of the sixth transistor is coupled to the second source/drain of the fourth transistor;
a seventh transistor, wherein a gate of the seventh transistor is coupled to the second source/drain of the sixth transistor, a first source/drain of the seventh transistor is configured to input the reference voltage level, and a second source/drain of the seventh transistor is coupled to the first node; and
an eighth transistor, wherein a gate of the eighth transistor is coupled to the second source/drain of the sixth transistor, a first source/drain of the eighth transistor is configured to input the reference voltage level, and a second source/drain of the eighth transistor is coupled to the second node.

### Claim 7 (depends on 1)

The shift register of claim 1, wherein the second pull-down unit comprises:
a ninth transistor, wherein a gate and a first source/drain of the ninth transistor are configured to input the second pull-down control signal;
a tenth transistor, wherein a gate of the tenth transistor is configured to input the first pull-down control signal, a first source/drain of the tenth transistor is configured to input the reference voltage level, and a second source/drain of the tenth transistor is coupled to the second source/drain of the ninth transistor;
an eleventh transistor, wherein a gate of the eleventh transistor is coupled to the first node, a first source/drain of the eleventh transistor is configured to input the reference voltage level, and a second source/drain of the eleventh transistor is coupled to the second source/drain of the ninth transistor;
a twelfth transistor, wherein a gate of the twelfth transistor is coupled to the second source/drain of the eleventh transistor, a first source/drain of the twelfth transistor is configured to input the reference voltage level, and a second source/drain of the twelfth transistor is coupled to the first node; and
a thirteenth transistor, wherein a gate of the thirteenth transistor is coupled to the second source/drain of the eleventh transistor, a first source/drain of the thirteenth transistor is configured to input the reference voltage level, and a second source/drain of the thirteenth transistor is coupled to the second node.

### Claim 8

A display device, comprising:
a display panel; and
a shift register configured to drive the display panel, the shift register comprising:
a pre-charge unit configured to receive a first input signal and a second input signal and output a pre-charge signal via a first node based on the first input signal and the second input signal;
a pull-up unit that is coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal and output a scan signal via a second node based on the pre-charge signal and the clock signal;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and control whether to pull down the scan signal to a reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and control whether to keep the scan signal at the reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
wherein a period of the first pull-down control signal and a period of the second pull-down control signal are in a range from 12 frames to 180 frames, and a time interval between a rising edge of the first pull-down control signal and a falling edge of the second pull-down control signal is in a range from 2 microseconds to 4 microseconds.

### Claim 9 (depends on 8)

The display device of claim 8, wherein the period of the first pull-down control signal is substantially the same as the period of the second pull-down control signal, and the period of the first pull-down control signal and the period of the second pull-down control signal are 120 frames.

### Claim 10

A display device, comprising:
a display panel; and
a gate driver configured to drive the display panel and having 1st-Nth stage shift registers, wherein the ith stage shift register of the 1st-Nth stage shift registers comprises:
a pre-charge unit configured to receive a first input signal and a second input signal and output a pre-charge signal via a first node based on the first input signal and the second input signal;
a pull-up unit that is coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal of a plurality of first clock signals and output an ith stage scan signal via a second node based on the pre-charge signal and the clock signal;
a first pull-down unit coupled to the pre-charge unit and the pull-up unit, the first pull-down unit configured to receive the pre-charge signal, a first pull-down control signal and a second pull-down control signal and control whether to pull down the ith stage scan signal to a reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal; and
a second pull-down unit coupled to the pre-charge unit and the pull-up unit, the second pull-down unit configured to receive the pre-charge signal, the first pull-down control signal and the second pull-down control signal and control whether to keep the ith stage scan signal at the reference voltage level based on the pre-charge signal, the first pull-down control signal and the second pull-down control signal;
wherein a period of the first pull-down control signal and a period of the second pull-down control signal are in a range from 12 frames to 180 frames, a time interval between a rising edge of the first pull-down control signal and a falling edge of the second pull-down control signal is in a range from 2 microseconds to 4 microseconds, N is an integer, and i is an integer from 1 to N.

### Claim 11 (depends on 10)

The display device of claim 10, wherein the period of the first pull-down control signal is substantially the same as the period of the second pull-down control signal, and the period of the first pull-down control signal and the period of the second pull-down control signal are 120 frames.

### Claim 12 (depends on 10)

The display device of claim 10, wherein the pre-charge unit of the ith stage shift register comprises:
a first transistor, wherein a gate of the first transistor is configured to receive a first input signal, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and
a second transistor, wherein a gate and a first source/drain of the second transistor are configured to receive a second input signal, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor;
wherein:
when i is 1 or 2 ,the first input signal is a starting signal, and the second input signal is an (i+2)th stage scan signal outputted by the (i+2)th stage shift register of the 1st-Nth stage shift registers;
when i is (N−1) or N, the first input signal is an (i−2)th stage scan signal outputted by the (i−2)th stage shift register of the 1st-Nth stage shift registers, and the second input signal is an ending signal;
when i is from 3 to (N−2), the first input signal is an (i−2)th stage scan signal outputted by the (i−2)th stage shift register of the 1st-Nth stage shift registers, and the second input signal is an (i+2)th stage scan signal outputted by the (i+2)th stage shift register of the 1st-Nth stage shift registers.

### Claim 13 (depends on 10)

The display device of claim 10, wherein the pre-charge unit of the ith stage shift register comprises:
a first transistor, wherein a gate of the first transistor is configured to receive a first input signal, a first source/drain of the first transistor is configured to receive a forward input signal, and a second source/drain of the first transistor is configured to output the pre-charge signal; and
a second transistor, wherein a gate of the second transistor is configured to receive a second input signal, a first source/drain of the second transistor is configured to receive a backward input signal, and a second source/drain of the second transistor is coupled to the second source/drain of the first transistor;
wherein:
when i is 1 or 2, the first input signal is a starting signal, and the second input signal is an (i+2)th stage scan signal outputted by the (i+2)th stage shift register of the 1st-Nth stage shift registers;
when i is (N−1) or N, the first input signal is an (i−2)th stage scan signal outputted by the (i−2)th stage shift register of the 1st-Nth stage shift registers, and the second input signal is an ending signal;
when i is from 3 to (N−2), the first input signal is an (i−2)thstage scan signal outputted by the (i−2)th stage shift register of the 1st-Nth stage shift registers, and the second input signal is an (i+2)th stage scan signal outputted by the (i+2)th stage shift register of the 1st-Nth stage shift registers.

### Claim 14 (depends on 10)

The display device of claim 10, wherein the pull-up unit of the ith stage shift register comprises:
a third transistor, wherein a gate of the third transistor is configured to receive the pre-charge signal, a first source/drain of the third transistor is configured to receive the clock signal, and a second source/drain of the third transistor is configured to output the scan signal; and
a capacitor, wherein a first terminal of the capacitor is coupled to the gate of the third terminal, and a second terminal of the capacitor is coupled to the second source/drain of the third transistor.