# US 10,121,437 B2 · Shift register and method for driving the same, gate driving circuit and display device

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- Number: US 10,121,437 B2
- Document ID: US10121437B2
- Status: Granted
- Kind: B2
- Application number: 15/131,527
- Filed: 2016-04-18
- Published: 2016-11-24
- Granted: 2018-11-06
- Earliest claimed: 2015-05-21
- Assignees: Boe Technology Group Co., Ltd.; Hefei Boe Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Hefei Boe Optoelectronics Technology Co., Ltd.
- Inventors: Honggang Gu; Xiaohe Li; Xianjie Shao
- Web page: https://patentgrep.com/patent/US10121437B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G11C 19/287: {Organisation of a multiplicity of shift registers}
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present invention provides a shift register and a method for driving the same, a gate driving circuit and a display device, and belongs to the field of display technology. The shift register of the present invention includes an input module, an output pulling-up module and a reset-and-noise-reducing module, wherein the input module is connected to a signal input terminal, a second clock signal input terminal, a power supply voltage terminal and a pulling-up node, the output pulling-up module is connected to a first clock signal input terminal, the pulling-up node and a signal output terminal, and the reset-and-noise-reducing module is connected to the second clock signal input terminal, a reset signal input terminal, a low voltage terminal, the pulling-up node and the signal output terminal. The shift register of the present invention has a simple structure, thereby facilitating the implementation of a narrow-bezel display device.

## Claims

### Claim 1

A shift register, comprising:
an input module, which comprises a first transistor and a fifth transistor, a first electrode of the first transistor being connected to a power supply voltage terminal, a second electrode of the first transistor being connected to a pulling-up node, a control electrode of the first transistor being connected to a signal input terminal, a first electrode of the fifth transistor being connected to the signal input terminal, a second electrode of the fifth transistor being connected to the pulling-up node, and a control electrode of the fifth transistor being connected to a second clock signal input terminal;
an output pulling-up module, which comprises a third transistor and a first storage capacitor, a first electrode of the third transistor being connected to a first clock signal input terminal, a second electrode of the third transistor being connected to a signal output terminal, a control electrode of the third transistor being connected to the pulling-up node, a first end of the first storage capacitor being connected to the pulling-up node, and a second end of the first storage capacitor being connected to the signal output terminal;
a reset-and-noise-reducing module, which comprises a second transistor, a fourth transistor and a second storage capacitor, a first electrode of the second transistor being connected to the pulling-up node, a second electrode of the second transistor being connected to a low voltage terminal, a control electrode of the second transistor being connected to a reset signal input terminal, a first electrode of the fourth transistor being connected to the signal output terminal, a second electrode of the fourth transistor being connected to the low voltage terminal, a control electrode of the fourth transistor being connected to a pulling-down node, a first end of the second storage capacitor being connected to the second clock signal input terminal, and a second end of the second storage capacitor being connected to the control electrode of the fourth transistor; and
a pulling-down module, which comprises a sixth transistor having a first electrode connected to the pulling-down node, a second electrode connected to the low voltage terminal, and a control electrode connected to the pulling-up node, wherein;
the reset-and-noise-reducing module is configured to turn on the fourth transistor by means of a bootstrapping of the second storage capacitor in a case where a reset signal inputted from the reset signal input terminal and a second clock signal inputted from the second clock signal input terminal are both at a first level, such that the signal output terminal is discharged to a second level via only the fourth transistor, the second level being different from the first level.

### Claim 2 (depends on 1)

The shift register according to claim 1, further comprising an assistant noise-reducing module, wherein,
the assistant noise-reducing module is connected to the first clock signal input terminal and the reset-and-noise-reducing module, and is used to assist the reset-and-noise-reducing module to perform the reset and noise reduction for the pulling-up node and the signal output terminal, under the control of a first clock signal inputted from the first clock signal input terminal.

### Claim 3 (depends on 2)

The shift register according to claim 2, wherein
the assistant noise-reducing module includes a third storage capacitor, and
a first end of the third storage capacitor is connected to the first clock signal input terminal, and a second end of the third storage capacitor is connected to the pulling-down node.

### Claim 4 (depends on 1)

A method for driving the shift register according to claim 1, the method comprising steps of:
inputting, in a pre-charging period, high-level signals from the signal input terminal of the input module and the second clock signal input terminal, and charging the pulling-up node through the power supply voltage inputted from the power supply voltage terminal and the high-level signal inputted from the signal input terminal;
turning on, in an outputting period, the output pulling-up module by the pulling-up node, and pulling up a voltage at the signal output terminal through a signal inputted from the first clock signal input terminal; and
with the second clock signal of the first level inputted from the second clock signal input terminal and the reset signal of the first level inputted from the reset signal input terminal, resetting the pulling-up node and reducing the noise thereof; through the low-voltage signal inputted from the low voltage terminal, and turning on the fourth transistor by means of a bootstrapping of the second storage capacitor such that the signal output terminal is discharged to the second level via only the fourth transistor, the second level being different from the first level.

### Claim 5 (depends on 1)

A gate driving circuit, comprising a plurality of cascaded shift registers according to claim 1.

### Claim 6 (depends on 5)

A display device, comprising the gate driving circuit according to claim 5.