# US 10,121,434 B2 · Stage circuit and scan driver using the same

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- Number: US 10,121,434 B2
- Document ID: US10121434B2
- Status: Granted
- Kind: B2
- Application number: 15/042,029
- Filed: 2016-02-11
- Published: 2016-10-20
- Granted: 2018-11-06
- Earliest claimed: 2015-04-14
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd
- Inventors: Jun Hyun Park; Sung Hwan Kim; Se Young Song; Kyoung Ju Shin; Jae Keun Lim
- Web page: https://patentgrep.com/patent/US10121434B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0465: Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

There is provided a stage circuit capable of minimizing a mounting area. The stage circuit includes: an output unit configured to supply a voltage of a first node, an i-th (i is a natural number) carry signal, and to supply an i-th scan signal in response to the voltage of the first node, a voltage of a second node, and a first clock signal, a controller configured to control the voltage of the second node in response to the first clock signal; a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage and a voltage of a first node of the previous stage, and a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage.

## Claims

### Claim 1

A stage circuit comprising:
an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th (i is a natural number) carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal;
a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal;
a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal; and
a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage supplied to a fourth input terminal,
wherein the pull-up unit comprises:
a first transistor having a first electrode connected to the second input terminal and a gate electrode connected to the third input terminal;
a second transistor having a first electrode and a gate electrode connected to a second electrode of the first transistor and a second electrode connected to the first node; and
a third transistor having a first electrode connected to the second electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal.

### Claim 2 (depends on 1)

The stage circuit of claim 1, wherein, when the carry signal of the previous stage is supplied, the second input terminal is set to have a lower voltage than that of the third input terminal.

### Claim 3 (depends on 1)

The stage circuit of claim 1, wherein the pull-up unit further comprises a fourth transistor having a first electrode and a gate electrode connected to the second input terminal and a second electrode connected to the first electrode of the first transistor.

### Claim 4 (depends on 1)

The stage circuit of claim 1, further comprising:
a first power source input terminal configured to receive a first off voltage; and
a second power source input terminal configured to receive a second off voltage different from the first off voltage.

### Claim 5 (depends on 4)

The stage circuit of claim 4, wherein the second off voltage is set to be lower than the first off voltage.

### Claim 6 (depends on 4)

The stage circuit of claim 4, wherein the output unit comprises:
a fifth transistor connected between the first input terminal and the second output terminal and having a gate electrode connected to the first node;
a sixth transistor connected between the second output terminal and the second power source input terminal and having a gate electrode connected to the second node;
a seventh transistor connected between the first input terminal and the third output terminal and having a gate electrode connected to the first node;
an eighth transistor connected between the third output terminal and the first power source input terminal and having a gate electrode connected to the second node; and
a ninth transistor connected between the third output terminal and the first power source input terminal and having a gate electrode connected to the fourth input terminal.

### Claim 7 (depends on 4)

The stage circuit of claim 4, wherein the controller comprises:
a tenth transistor having a first electrode and a gate electrode connected to the first input terminal;
an 11th transistor connected between a second electrode of the tenth transistor and the second power source input terminal and having a gate electrode connected to the second output terminal;
a 12th transistor connected between the first input terminal and the second node and having a gate electrode connected to the second electrode of the tenth transistor; and
a 13th transistor connected between the second node and the second power source input terminal and having a gate electrode connected to the second output terminal.

### Claim 8 (depends on 4)

The stage circuit of claim 4, wherein the pull-down unit comprises:
a 14th transistor and a 15th transistor serially connected between the first node and the second power source input terminal and having gate electrodes connected to the second node;
a 16th transistor connected between the second output terminal and the second power source input terminal and having a gate electrode connected to the fourth input terminal; and
a 17th transistor and an 18th transistor serially connected between the first node and the second power source input terminal and having gate electrodes connected to the fourth input terminal.

### Claim 9 (depends on 1)

The stage circuit of claim 1,
wherein a carry signal of the previous stage is an (i−1)-th carry signal, and
wherein a carry signal of the next stage is an (i+1)-th carry signal.

### Claim 10

A stage circuit comprising:
an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th (i is a natural number) carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal;
a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal;
a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal; and
a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage supplied to a fourth input terminal,
wherein the pull-up unit comprises:
a first transistor having a first electrode connected to the second input terminal and a gate electrode connected to the third input terminal;
a second transistor having a first electrode and a gate electrode connected to a second electrode of the first transistor and a second electrode connected to the first node;
a third transistor having a first electrode connected to the first electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal; and
a fourth transistor having a first electrode and a gate electrode connected to the second input terminal and a second electrode connected to the first electrode of the first transistor.

### Claim 11

A scan driver including stages respectively connected to scan lines and outputting one of a plurality of clock signals input from an external source as scan signals, wherein an i-th (i is a natural number) stage circuit among the stages comprises:
an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal;
a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal;
a pull-up unit configured to control the voltage of the first node in response to an (i−1)-th carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal; and
a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and an (i+1)-th carry signal of a next stage supplied to a fourth input terminal,
wherein the pull-up unit comprises:
a first transistor having a first electrode connected to the second input terminal and a gate electrode connected to the third input terminal;
a second transistor having a first electrode and a gate electrode connected to a second electrode of the first transistor and a second electrode connected to the first node; and
a third transistor having a first electrode connected to the second electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal.

### Claim 12 (depends on 11)

The scan driver of claim 11, wherein, when the (i−1)-th carry signal is supplied, the second input terminal is set to have a lower voltage than that of the third input terminal.

### Claim 13 (depends on 11)

The scan driver of claim 11, wherein the pull-up unit further comprises a fourth transistor having a first electrode and a gate electrode connected to the second input terminal and a second electrode connected to the first electrode of the first transistor.

### Claim 14

A scan driver including stages respectively connected to scan lines and outputting one of a plurality of clock signals input from an external source as scan signals, wherein an i-th (i is a natural number) stage circuit among the stages comprises:
an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal;
a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal;
a pull-up unit configured to control the voltage of the first node in response to an (i−1)-th carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal; and
a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and an (i+1)-th carry signal of a next stage supplied to a fourth input terminal,
wherein the pull-up unit comprises:
a first transistor having a first electrode connected to the second input terminal and a gate electrode connected to the third input terminal;
a second transistor having a first electrode and a gate electrode connected to a second electrode of the first transistor and a second electrode connected to the first node;
a third transistor having a first electrode connected to the first electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal; and
a fourth transistor having a first electrode and a gate electrode connected to the second input terminal and a second electrode connected to the first electrode of the first transistor.