# US 10,121,433 B2 · GOA circuit and method for driving the same and LCD

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- Number: US 10,121,433 B2
- Document ID: US10121433B2
- Status: Granted
- Kind: B2
- Application number: 14/895,601
- Filed: 2015-11-06
- Published: 2017-09-07
- Granted: 2018-11-06
- Earliest claimed: 2015-09-23
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.; Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.; Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Juncheng Xiao; Ronglei Dai; Shangcao Cao; Yao Yan
- Web page: https://patentgrep.com/patent/US10121433B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G11C 19/184: {with field-effect transistors, e.g. MOS-FET}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0218: with collection of electrodes in groups for n-dimensional addressing
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/026: Arrangements or methods related to booting a display
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A gate on array (GOA) circuit for used in an LCD includes GOA units connected in cascade. An Nth GOA unit includes an Nth stage-transmittance circuit, an Nth Q-node controlling circuit, an Nth P-node controlling circuit, an Nth outputting circuit, and a first switch circuit where N is a positive integer. The first switch circuit connected to the Nth scanning line, for inputting an enabling signal to the Nth scanning line before the LCD shows images so as to turn on a TFT in a pixel which the Nth scanning line is connected to. The benefit of the function is that the display does not leak electricity when the black screen is woken up and that the stability of the circuit is enhanced at the same time.

## Claims

### Claim 1

A gate on array (GOA) circuit for liquid crystal display (LCD), comprising: a plurality of GOA units connected in cascade, an Nth GOA unit comprising an Nth stage-transmittance circuit, an Nth Q-node controlling circuit, an Nth P-node controlling circuit, an Nth outputting circuit, and a first switch circuit where N is a positive integer;
wherein the Nth stage-transmittance circuit is connected to the Nth Q-node controlling circuit, the Nth Q-node controlling circuit is connected to the Nth outputting circuit via a Q node, the Nth stage-transmittance circuit is connected to the Nth P-node controlling circuit, the Nth P-node controlling circuit is connected to the Nth outputting circuit via a P node, and further, the Nth outputting circuit is connected to the Nth scanning line;
the first switch circuit connected to the Nth scanning line, for inputting an enabling signal to the Nth scanning line before the LCD shows images so as to turn on a thin-film transistor (TFT) in a pixel which the Nth scanning line is connected to,
wherein the Nth Q-node controlling circuit comprises:
a seventh TFT, a gate of the seventh TFT receiving an (N−2)th clock signal, a drain of the seventh TFT receiving an (N−2)th scanning signal in a period of forward scanning or receiving an (N+2)th scanning signal in a period of reverse scanning, and a source of the seventh TFT connected to the Q node;
an eighth TFT, a gate of the eighth TFT receiving an (N−2)th scanning signal G(N−2), a drain of the eighth TFT connected to the P node, and a source of the eighth TFT receiving a signal at low level;
a ninth TFT, a gate of the ninth TFT connected to the drain of the eighth TFT, a drain of the ninth TFT connected to the source of the seventh TFT, and a source of the ninth TFT connected to a signal at low level.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the first switch circuit comprises a first TFT, a source of the first TFT is connected to the Nth scanning line, a gate of the first TFT receives a first enabling signal at high level before the LCD shows images so as to turn on the source of the first TFT and a drain of the first TFT and transmits a signal at high level to the Nth scanning line so as to turn on the TFT in the pixel which the Nth scanning line is connected to.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the GOA unit further comprises a second switch circuit;
the second switch circuit comprising a second TFT, a drain of the second TFT connected to the Nth scanning line, and the second switch circuit receiving a second enabling signal at high level from a gate of the second TFT so as to turn on the source of the second TFT and a drain of the second TFT and transmitting a signal at low level to the Nth scanning line after transmitting a signal at high level to the Nth scanning line so as to turn off the TFT in the pixel which the Nth scanning line is connected to.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the Nth stage-transmittance circuit comprises a third TFT, a fourth TFT, a fifth TFT, and a sixth TFT;
a gate of the third TFT and a gate of the fourth TFT receiving a forward scanning controlling signal, for receiving an (N−2)th scanning signal through the third TFT in the period of forward scanning, and for receiving an (N+1)th clock signal through the fourth TFT;
a gate of the fifth TFT and a gate of the sixth TFT receiving a reverse scanning controlling signal, for receiving an (N+2)th scanning signal through the fifth TFT in the period of reverse scanning, and for receiving an (N−1)th clock signal through the sixth TFT.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the Nth P-node controlling circuit comprises:
a tenth TFT, a gate of the tenth TFT receiving an (N+1)th clock signal in the period of forward scanning or receiving an (N−2)th clock signal in the period of reverse scanning, a drain of the tenth TFT receiving a signal at high level, and a source of the tenth TFT connected to the P node;
an eleventh TFT, a gate of the eleventh TFT connected to the Q node, a drain of the eleventh TFT connected to the P node, and a source of the eleventh TFT receiving a signal at low level.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the Nth P-node controlling circuit further comprises:
a twelfth TFT, a gate of the twelfth receiving the first enabling signal, a drain of the twelfth connected to the P node, and a source of the twelfth TFT receiving a signal at low level.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the Nth outputting circuit comprises:
a thirteenth TFT, a gate of the thirteenth TFT connected to the Q node, a drain of the thirteenth TFT receiving an Nth clock signal, and a source of the thirteenth TFT connected to the Nth scanning line;
a fourteenth TFT, a gate of the fourteenth TFT connected to the P node, a drain of the fourteenth TFT connected to the Nth scanning line, and a source of the fourteenth TFT connected to a signal at low level.

### Claim 8

A liquid crystal display (LCD) comprising a gate on array (GOA) circuit, the GOA circuit comprising: a plurality of GOA units connected in cascade, an Nth GOA unit comprising an Nth stage-transmittance circuit, an Nth Q-node controlling circuit, an Nth P-node controlling circuit, an Nth outputting circuit, and a first switch circuit where N is a positive integer;
wherein the Nth stage-transmittance circuit is connected to the Nth Q-node controlling circuit, the Nth Q-node controlling circuit is connected to the Nth outputting circuit via a Q node, the Nth stage-transmittance circuit is connected to the Nth P-node controlling circuit, the Nth P-node controlling circuit is connected to the Nth outputting circuit via a P node, and further, the Nth outputting circuit is connected to the Nth scanning line;
the first switch circuit connected to the Nth scanning line, for inputting an enabling signal to the Nth scanning line before the LCD shows images so as to turn on a thin-film transistor (TFT) in a pixel which the Nth scanning line is connected to,
wherein the Nth Q-node controlling circuit comprises:
a seventh TFT, a gate of the seventh TFT receiving an (N−2)th clock signal, a drain of the seventh TFT receiving an (N−2)th scanning signal in a period of forward scanning or receiving an (N+2)th scanning signal in a period of reverse scanning, and a source of the seventh TFT connected to the Q node;
an eighth TFT, a gate of the eighth TFT receiving an (N−2)th scanning signal G(N−2), a drain of the eighth TFT connected to the P node, and a source of the eighth TFT receiving a signal at low level;
a ninth TFT, a gate of the ninth TFT connected to the drain of the eighth TFT, a drain of the ninth TFT connected to the source of the seventh TFT, and a source of the ninth TFT connected to a signal at low level.

### Claim 9 (depends on 8)

The LCD of claim 8, wherein the first switch circuit comprises a first TFT, a source of the first TFT is connected to the Nth scanning line, a gate of the first TFT receives a first enabling signal at high level before the LCD shows images so as to turn on the source of the first TFT and a drain of the first TFT and transmits a signal at high level to the Nth scanning line so as to turn on the TFT in the pixel which the Nth scanning line is connected to.

### Claim 10 (depends on 8)

The LCD of claim 8, wherein the GOA unit further comprises a second switch circuit;
the second switch circuit comprising a second TFT, a drain of the second TFT connected to the Nth scanning line, and the second switch circuit receiving a second enabling signal at high level from a gate of the second TFT so as to turn on the source of the second TFT and a drain of the second TFT and transmitting a signal at low level to the Nth scanning line after transmitting a signal at high level to the Nth scanning line so as to turn off the TFT in the pixel which the Nth scanning line is connected to.

### Claim 11 (depends on 8)

The LCD of claim 8, wherein the Nth stage-transmittance circuit comprises a third TFT, a fourth TFT, a fifth TFT, and a sixth TFT;
a gate of the third TFT and a gate of the fourth TFT receiving a forward scanning controlling signal, for receiving an (N−2)th scanning signal through the third TFT in the period of forward scanning, and for receiving an (N+1)th clock signal through the fourth TFT;
a gate of the fifth TFT and a gate of the sixth TFT receiving a reverse scanning controlling signal, for receiving an (N+2)th scanning signal through the fifth TFT in the period of reverse scanning, and for receiving an (N−1)th clock signal through the sixth TFT.

### Claim 12 (depends on 8)

The LCD of claim 8, wherein the Nth P-node controlling circuit comprises:
a tenth TFT, a gate of the tenth TFT receiving an (N+1)th clock signal in the period of forward scanning or receiving an (N−2)th clock signal in the period of reverse scanning, a drain of the tenth TFT receiving a signal at high level, and a source of the tenth TFT connected to the P node;
an eleventh TFT, a gate of the eleventh TFT connected to the Q node, a drain of the eleventh TFT connected to the P node, and a source of the eleventh TFT receiving a signal at low level.

### Claim 13 (depends on 12)

The LCD of claim 12, wherein the Nth P-node controlling circuit further comprises:
a twelfth TFT, a gate of the twelfth receiving the first enabling signal, a drain of the twelfth connected to the P node, and a source of the twelfth TFT receiving a signal at low level.

### Claim 14 (depends on 8)

The LCD of claim 8, wherein the Nth outputting circuit comprises:
a thirteenth TFT, a gate of the thirteenth TFT connected to the Q node, a drain of the thirteenth TFT receiving an Nth clock signal, and a source of the thirteenth TFT connected to the Nth scanning line;
a fourteenth TFT, a gate of the fourteenth TFT connected to the P node, a drain of the fourteenth TFT connected to the Nth scanning line, and a source of the fourteenth TFT connected to a signal at low level.