# US 10,121,429 B2 · Active matrix substrate, display panel, and display device including the same

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- Number: US 10,121,429 B2
- Document ID: US10121429B2
- Status: Granted
- Kind: B2
- Application number: 14/916,224
- Filed: 2014-08-27
- Published: 2016-07-28
- Granted: 2018-11-06
- Earliest claimed: 2013-09-04
- Assignees: Sharp Kabushiki Kaisha
- Applicants: Sharp Kabushiki Kaisha
- Inventors: Kohhei Tanaka; Hidefumi Yoshida
- Web page: https://patentgrep.com/patent/US10121429B2

## CPC

- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G02F 1/13306: {Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence)}
- G02F 1/133514: {Colour filters}
- G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)}
- G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)}
- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0804: Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
- G09G 2310/0248: Precharge or discharge of column electrodes before or after applying exact column voltages
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/021: Power management, e.g. power saving
- G09G 2340/0442: Handling or displaying different aspect ratios, or changing the aspect ratio
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present invention addresses the problem of reducing power consumption when switching a gate line between a selected state and a non-selected state, and of providing a narrower frame for an active matrix substrate. A gate driver (11) that scans each gate line is formed inside a display area in an active matrix substrate (20a) having gate lines (13G) and data lines formed therein. The gate driver (11) switches the gate line to either a selected state or a non-selected state, in accordance with a control signal supplied via a line (15L). The gate driver (11) includes a high-charge drive circuit (11a), a low-charge drive circuit (11b), and a shift register (11c). The high-charge drive circuit is supplied with a first DC voltage signal corresponding to the selected state via the line (15L), and charges the gate line to the potential of the first DC voltage signal. The low-charge drive circuit (11b) is supplied with a second DC voltage signal corresponding to the non-selected state, and charges the gate line to the potential of the second DC voltage signal.

## Claims

### Claim 1

An active matrix substrate comprising a plurality of gate lines, and a plurality of data lines that intersect the plurality of gate lines, the active matrix substrate including a display area, the active matrix substrate further comprising:
a plurality of drive circuits provided for the plurality of gate lines, respectively, each of the plurality of drive circuits switching a state of a respective gate line according to a control signal supplied thereto, to either one of a selected state for selection of the respective gate line and a non-selection state for non-selection of the respective gate line, wherein
each of the plurality of drive circuits includes a first charging driving portion and a second charging driving portion,
the first charging driving portion includes a switching element that is supplied with a first DC voltage signal corresponding to the selected state, the switching element of the first charging driving portion charging the gate line to a potential of the first DC voltage signal,
the second charging driving portion includes a switching element that is supplied with a second DC voltage signal corresponding to the non-selected state and having a voltage lower than that of the first DC voltage signal, the switching element of the second charging driving portion charging the respective gate line to a potential of the second DC voltage signal, and
at least one of the first charging driving portion and the second charging driving portion is in the display area,
the gate lines are N in number (N is an integer),
a first start pulse signal is input to the first charging driving portion in the first drive circuit provided with respect to the first gate line, among the drive circuits, and the first charging driving portion charges the first gate line to the potential of the first DC voltage signal according to the first start pulse signal,
a second start pulse signal different from the first start pulse signal is input to the second charging driving portion in the first drive circuit, and the second charging driving portion charges the first gate line to the potential of the second DC voltage signal according to the second start pulse signal,
the first charging driving portion in the n'th drive circuit provided with respect to the n'th gate line (2≤n≤N), among the drive circuits, is connected to the n−1'th gate line, and the first charging driving portion charges the n'th gate line to the potential of the first DC voltage signal according to the potential of the n−1'th gate line, and
the second charging driving portion in the n'th drive circuit is connected to the second charging driving portion in the drive circuit provided with respect to the n−1'th gate line, and charges the n'th gate line to the potential of the second DC voltage signal according to the output potential of the second charging driving portion in the n−1'th drive circuit.

### Claim 2 (depends on 1)

A display panel comprising:
the active matrix substrate according to claim 1;
a pixel electrode on the active matrix substrate;
a counter substrate including a common electrode and a color filter; and
a liquid crystal layer between the active matrix substrate and the counter substrate.

### Claim 3 (depends on 2)

A display device comprising:
the display panel according to claim 2;
a display control circuit that outputs a control signal including a clock signal to the display panel; and
a power source circuit that supplies a DC voltage signal to the display panel.
