# US 10,121,403 B2 · Gate turn on voltage compensating circuit, display panel, driving method and display apparatus

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- Number: US 10,121,403 B2
- Document ID: US10121403B2
- Status: Granted
- Kind: B2
- Application number: 15/086,836
- Filed: 2016-03-31
- Published: 2017-03-16
- Granted: 2018-11-06
- Earliest claimed: 2015-09-15
- Assignees: Boe Technology Group Co., Ltd.; Chongqing Boe Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Chongqing Boe Optoelectronics Technology Co., Ltd.
- Inventors: Xu Lu; Yih Jen Hsu; Fei Shang; Haijun Qiu; Lijun Xiao; Shuai Hou
- Web page: https://patentgrep.com/patent/US10121403B2

## CPC

- G09G 3/2007: {Display of intermediate tones}
- G09G 3/3225: using an active matrix
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 3/3696: {Generation of voltages supplied to electrode drivers}
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/066: Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
- G09G 2310/067: Special waveforms for scanning, where no circuit details of the gate driver are given
- G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present disclosure provides a gate turn on voltage compensating circuit, a display panel, a driving method and a display apparatus thereof. The gate turn on voltage compensating circuit includes a voltage generation module, a clock control module and a chamfering module. The voltage generation module is used for correspondingly outputting generated first voltage signal and second voltage signal to a first voltage input terminal and a second voltage input terminal of the chamfering module; the clock control module is used for controlling the chamfering module to output corresponding chamfered voltage signals in the corresponding time periods, so that the chamfering depths of gate turn on voltage signals input correspondingly to respective gate drive chips in different time periods are different.

## Claims

### Claim 1

A gate turn on voltage compensating circuit, comprising a voltage generation module, a clock control module and a chamfering module,
the voltage generation module being used for generating a first voltage signal and a second voltage signal and correspondingly outputting, through a first voltage output terminal and a second voltage output terminal thereof, the generated first and second voltage signals to a first voltage input terminal and a second voltage input terminal of the chamfering module;
a first output terminal of the clock control module being connected with a first control terminal of the chamfering module, a second output terminal of the clock control module being connected with a second control terminal of the chamfering module; and
the chamfering module outputting the second voltage signal at a first time period and outputting a chamfered gate turn on voltage signal at a second time period under the control of the first output terminal and the second output terminal of the clock control module based on the first voltage signal and the second voltage signal.

### Claim 2 (depends on 1)

The gate turn on voltage compensating circuit according to claim 1, wherein the chamfering module comprises a chamfering time control unit, a chamfering depth control unit and a output control unit, wherein
a first control terminal of the chamfering time control unit is connected with the first output terminal of the clock control module, a second control terminal thereof is connected with a reference voltage terminal, a first input terminal thereof is connected with the second voltage output terminal of the voltage generation module, a second input terminal thereof is connected with a ground signal terminal, and an output terminal thereof is connected with a first control terminal and a first input terminal of the output control unit respectively, and the chamfering time control unit is used for controlling the chamfering time for outputting the chamfered gate turn on voltage signal under the control of the first output terminal of the clock control module and the reference voltage terminal;
a first control terminal of the chamfering depth control unit is connected with the second output terminal of the clock control module, a second control terminal thereof is connected with the reference voltage terminal, a first input terminal thereof is connected with the first voltage output terminal of the voltage generation module, a second input terminal thereof is connected with the ground signal terminal, and an output terminal thereof with a second input terminal of the output control unit, and the chamfering depth control unit is used for outputting the chamfered gate turn on voltage signals of different chamfering depths under the control of the second output terminal of the clock control module and the reference voltage terminal;
a second control terminal of the output control unit is connected with the first voltage output terminal of the voltage generation module, a third input terminal thereof is connected with the ground signal terminal, and an output terminal thereof is connected with a gate turn on voltage input terminal, and the output control unit is used for selecting, through the gate turn on voltage input terminal, to output the second voltage signal generated by the voltage generation module or the chamfered gate turn on voltage signal under the control of the output terminal of the chamfering time control unit and the first voltage output terminal of the voltage generation module.

### Claim 3 (depends on 2)

The gate turn on voltage compensating circuit according to claim 2, wherein the chamfering time control unit comprises a first comparator, a first switching transistor, a second switching transistor and a first resistor, wherein
a first input terminal of the first comparator is connected with the first output terminal of the clock control module, a second input terminal thereof is connected with the reference voltage terminal, and an output terminal thereof is connected with a gate of the first switching transistor and a gate of the second switching transistor, respectively;
a source of the first switching transistor is connected with the second voltage output terminal of the voltage generation module, a drain thereof is connected with a drain of the second switching transistor and the first input terminal of the output control unit, respectively;
a source of the second switching transistor is connected with one end of the first resistor;
the other end of the first resistor is connected with the ground signal terminal.

### Claim 4 (depends on 3)

The gate turn on voltage compensating circuit according to claim 3, wherein the first switching transistor is an N-type transistor, and the second switching transistor is a P-type transistor.

### Claim 5 (depends on 2)

The gate turn on voltage compensating circuit according to claim 2, wherein the output control unit comprises a second comparator, a third switching transistor, a fourth switching transistor and a storage capacitor, wherein
a first input terminal of the second comparator is connected with the output terminal of the chamfering time control unit and a source of the third switching transistor, respectively, a second input terminal thereof is connected with the first voltage output terminal of the voltage generation module, and an output terminal thereof is connected with a gate of the third switching transistor and a gate of the fourth switching transistor, respectively;
a drain of the third switching transistor is connected with the gate turn on voltage input terminal;
a source of the fourth switching transistor is connected with the output terminal of the chamfering depth control unit, and a drain thereof is connected with the gate turn on voltage input terminal;
the storage capacitor is connected between the ground signal terminal and the gate turn on voltage input terminal.

### Claim 6 (depends on 5)

The gate turn on voltage compensating circuit according to claim 5, wherein the third switching transistor is an N-type transistor, and the fourth switching transistor is a P-type transistor.

### Claim 7 (depends on 2)

The gate turn on voltage compensating circuit according to claim 2, wherein the chamfering depth control unit comprises a second resistor, a third resistor, a third comparator, a fifth switching transistor, a sixth switching transistor and a fourth resistor, wherein
one end of the second resistor is connected with the first voltage output terminal of the voltage generation module, and the other end thereof is connected with one end of the third resistor and a source of the fifth switching transistor, respectively;
the other end of the third resistor is connected with the ground signal terminal;
a first input terminal of the third comparator is connected with the second output terminal of the clock control module, a second input terminal thereof is connected with the reference voltage terminal, and an output terminal thereof is connected with a gate of the fifth switching transistor and a gate of the sixth switching transistor, respectively;
a drain of the fifth switching transistor is connected with a drain of the sixth switching transistor and the second input terminal of the output control unit, respectively;
a source of the sixth switching transistor is connected with one end of the fourth resistor;
the other end of the fourth resistor is connected with the ground signal terminal.

### Claim 8 (depends on 7)

The gate turn on voltage compensating circuit according to claim 7, wherein the fifth switching transistor is an N-type transistor, and the sixth switching transistor is a P-type transistor.

### Claim 9 (depends on 1)

The gate turn on voltage compensating circuit according to claim 1, wherein the gate turn on voltage compensating circuit is arranged on a printed circuit board.

### Claim 10 (depends on 1)

A display panel, comprising a plurality of gate lines located in a display area, a plurality of gate drive chips for inputting gate turn on voltage signals to the gate lines, and the gate turn on voltage compensating circuit according to claim 1, wherein
the gate drive chips are connected in cascade;
the gate turn on voltage compensating circuit is used for inputting the corresponding chamfered gate turn on voltage signal to the gate drive chip of a first stage at the chamfering time.

### Claim 11 (depends on 10)

The display panel according to claim 10, wherein the plurality of gate drive chips forms two groups of gate drive chips which are symmetrically distributed at two terminals of the gate lines, and the gate drive chip of the last stage in the first group of gate drive chips and the gate drive chip of the last stage in the second group of gate drive chips are connected in cascade;
the gate turn on voltage compensating circuit is used for inputting the corresponding chamfered gate turn on voltage signal to the gate drive chip of the first stage in the first group of gate drive chips at the chamfering time.

### Claim 12 (depends on 11)

The display panel according to claim 11, wherein the chamfering module comprises a chamfering time control unit, a chamfering depth control unit and a output control unit, wherein
a first control terminal of the chamfering time control unit is connected with the first output terminal of the clock control module, a second control terminal thereof is connected with a reference voltage terminal, a first input terminal thereof is connected with the second voltage output terminal of the voltage generation module, a second input terminal thereof is connected with a ground signal terminal, and an output terminal thereof is connected with a first control terminal and a first input terminal of the output control unit respectively, and the chamfering time control unit is used for controlling the chamfering time for outputting the chamfered gate turn on voltage signal under the control of the first output terminal of the clock control module and the reference voltage terminal;
a first control terminal of the chamfering depth control unit is connected with the second output terminal of the clock control module, a second control terminal thereof is connected with the reference voltage terminal, a first input terminal thereof is connected with the first voltage output terminal of the voltage generation module, a second input terminal thereof is connected with the ground signal terminal, and an output terminal thereof with a second input terminal of the output control unit, and the chamfering depth control unit is used for outputting the chamfered gate turn on voltage signals of different chamfering depths under the control of the second output terminal of the clock control module and the reference voltage terminal;
a second control terminal of the output control unit is connected with the first voltage output terminal of the voltage generation module, a third input terminal thereof is connected with the ground signal terminal, and an output terminal thereof is connected with a gate turn on voltage input terminal, and the output control unit is used for selecting, through the gate turn on voltage input terminal, to output the second voltage signal generated by the voltage generation module or the chamfered gate turn on voltage signal under the control of the output terminal of the chamfering time control unit and the first voltage output terminal of the voltage generation module.

### Claim 13 (depends on 12)

The display panel according to claim 12, wherein the chamfering time control unit comprises a first comparator, a first switching transistor, a second switching transistor and a first resistor, wherein
a first input terminal of the first comparator is connected with the first output terminal of the clock control module, a second input terminal thereof is connected with the reference voltage terminal, and an output terminal thereof is connected with a gate of the first switching transistor and a gate of the second switching transistor, respectively;
a source of the first switching transistor is connected with the second voltage output terminal of the voltage generation module, a drain thereof is connected with a drain of the second switching transistor and the first input terminal of the output control unit, respectively;
a source of the second switching transistor is connected with one end of the first resistor;
the other end of the first resistor is connected with the ground signal terminal.

### Claim 14 (depends on 13)

The display panel according to claim 13, wherein the first switching transistor is an N-type transistor, and the second switching transistor is a P-type transistor.

### Claim 15 (depends on 12)

The display panel according to claim 12, wherein the output control unit comprises a second comparator, a third switching transistor, a fourth switching transistor and a storage capacitor, wherein
a first input terminal of the second comparator is connected with the output terminal of the chamfering time control unit and a source of the third switching transistor, respectively, a second input terminal thereof is connected with the first voltage output terminal of the voltage generation module, and an output terminal thereof is connected with a gate of the third switching transistor and a gate of the fourth switching transistor, respectively;
a drain of the third switching transistor is connected with the gate turn on voltage input terminal;
a source of the fourth switching transistor is connected with the output terminal of the chamfering depth control unit, and a drain thereof is connected with the gate turn on voltage input terminal;
the storage capacitor is connected between the ground signal terminal and the gate turn on voltage input terminal.

### Claim 16 (depends on 15)

The display panel according to claim 15, wherein the third switching transistor is an N-type transistor, and the fourth switching transistor is a P-type transistor.

### Claim 17 (depends on 12)

The display panel according to claim 12, wherein the chamfering depth control unit specifically comprises a second resistor, a third resistor, a third comparator, a fifth switching transistor, a sixth switching transistor and a fourth resistor, wherein
one end of the second resistor is connected with the first voltage output terminal of the voltage generation module, and the other end thereof is connected with one end of the third resistor and a source of the fifth switching transistor, respectively;
the other end of the third resistor is connected with the ground signal terminal;
a first input terminal of the third comparator is connected with the second output terminal of the clock control module, a second input terminal thereof is connected with the reference voltage terminal, and an output terminal thereof is connected with a gate of the fifth switching transistor and a gate of the sixth switching transistor, respectively;
a drain of the fifth switching transistor is connected with a drain of the sixth switching transistor and the second input terminal of the output control unit, respectively;
a source of the sixth switching transistor is connected with one end of the fourth resistor;
the other end of the fourth resistor is connected with the ground signal terminal.

### Claim 18 (depends on 17)

The display panel according to claim 17, wherein the fifth switching transistor is an N-type transistor, and the sixth switching transistor is a P-type transistor.

### Claim 19 (depends on 10)

A driving method of the display panel according to claim 10, comprising:
within the display time of one frame, inputting, by the gate turn on voltage compensating circuit, shallowly-chamfered gate turn on voltage signals to gate drive chips of former m stages in the plurality of gate drive chips connected in cascade, and inputting deeply-chamfered gate turn on voltage signals to gate drive chips of remaining stages.

### Claim 20 (depends on 10)

A display apparatus, comprising the display panel according to claim 10.