# US 10,121,220 B2 · System and method for creating aliased mappings to minimize impact of cache invalidation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,220 B2 - Document ID: US10121220B2 - Status: Granted - Kind: B2 - Application number: 14/698,024 - Filed: 2015-04-28 - Published: 2016-11-03 - Granted: 2018-11-06 - Earliest claimed: 2015-04-28 - Assignees: NVIDIA Corporation - Applicants: Nvidia Corporation - Inventors: Jeffrey Bolz - Web page: https://patentgrep.com/patent/US10121220B2 ## CPC - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F 9/3885: {using a plurality of independent parallel functional units} - G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence) - G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)} - G06F 12/0888: using selective caching, e.g. bypass - G06T 15/005: {General purpose rendering architectures} - G06T 15/04: Texture mapping - G09G 5/395: Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence) - G06F 2212/1024: Latency reduction - G06F 2212/1041: Resource optimization - G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device - G09G 5/39: Control of the bit-mapped memory - G09G 2340/10: Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels - G09G 2360/121: using a cache memory - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A parallel processor and a method of reducing texture cache invalidation are disclosed. In one embodiment, the parallel processor includes a cache configured to receive lines of data; and a parallel execution unit associated with the cache and configured to execute parallel counterparts of an operation. The parallel counterparts, when executed, are configured to create, in the cache, corresponding aliases of a line of data pertaining to the operation such that the parallel counterparts are operable to invalidate only the corresponding aliases. ## Claims ### Claim 1 A parallel processor, comprising: a cache configured to receive data pertaining to an operation; and a parallel execution unit associated with said cache and configured to execute parallel counterparts of said operation such that, when executed in parallel, said parallel counterparts is configured to create in said cache multiple aliases for said data, each of said multiple aliases corresponding to a different copy of said data, wherein each of said parallel counterparts is operable to invalidate only one of said different copies of said data. ### Claim 2 (depends on 1) The parallel processor as recited in claim 1 wherein said multiple aliases are created in said cache by executing a texture load. ### Claim 3 (depends on 1) The parallel processor as recited in claim 1 wherein said parallel processor is a graphics processing unit. ### Claim 4 (depends on 1) The parallel processor as recited in claim 1 wherein said operation includes blending color values to accomplish transparency. ### Claim 5 (depends on 1) The parallel processor as recited in claim 1 wherein said parallel counterparts are configured to store said multiple aliases by executing a surface store. ### Claim 6 (depends on 1) The parallel processor as recited in claim 1 wherein said operation prevents said parallel counterparts from working on a same portion of said data. ### Claim 7 (depends on 1) The parallel processor as recited in claim 1 wherein said multiple aliases correspond to said parallel counterparts based on a number of said parallel counterparts using said multiple aliases. ### Claim 8 A method of reducing an impact of cache invalidation, comprising: executing, using a parallel processor, parallel counterparts of a surface operation in parallel, said operation pertaining to data in a cache; causing, with said parallel counterparts, multiple aliases for said data to be loaded into said cache, each of said multiple aliases corresponding to a different copy of said data; and allowing each of said parallel counterparts of said operation to invalidate only one of said different copies of said data. ### Claim 9 (depends on 8) The method as recited in claim 8 wherein said cache is associated with a parallel processor and said multiple aliases are loaded by executing a texture load. ### Claim 10 (depends on 8) The method as recited in claim 8 wherein said parallel processor is a graphics processing unit. ### Claim 11 (depends on 8) The method as recited in claim 8 wherein said cache is a texture cache. ### Claim 12 (depends on 11) The method as recited in claim 11 wherein said multiple aliases are stored by executing a surface store. ### Claim 13 (depends on 8) The method as recited in claim 8 wherein said operation prevents said parallel counterparts from working on a same portion of said data. ### Claim 14 (depends on 8) The method as recited in claim 8 wherein said multiple aliases correspond to said parallel counterparts based on a number of said parallel counterparts using said multiple aliases. ### Claim 15 A non-transitory computer readable medium storing a surface operation that is executable by a processor, said surface operation comprising: executing parallel counterparts of said surface operation in parallel, said operation pertaining to data in a cache; causing, with said parallel counterparts, multiple aliases for said data to be loaded into said cache, each of said multiple aliases corresponding to a different copy of said data; and allowing each of said parallel counterparts of said operation to invalidate only one of said different copies of said data. ### Claim 16 (depends on 15) The non-transitory computer readable medium as recited in claim 15 wherein said multiple aliases are loaded by executing a texture load. ### Claim 17 (depends on 15) The non-transitory computer readable medium as recited in claim 15 wherein said cache is a texture cache. ### Claim 18 (depends on 15) The non-transitory computer readable medium as recited in claim 15 wherein said multiple aliases are stored by executing a surface store. ### Claim 19 (depends on 15) The non-transitory computer readable medium as recited in claim 15 wherein said operation prevents said parallel counterparts from working on a same portion of said data. ### Claim 20 (depends on 15) The non-transitory computer readable medium as recited in claim 15 wherein said multiple aliases correspond to said parallel counterparts based on a number of said parallel counterparts using said multiple aliases.