# US 10,121,011 B2 · Apparatus, method and article of manufacture for partially resisting hardware trojan induced data leakage in sequential logics > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,011 B2 - Document ID: US10121011B2 - Status: Granted - Kind: B2 - Application number: 15/397,142 - Filed: 2017-01-03 - Published: 2018-05-17 - Granted: 2018-11-06 - Earliest claimed: 2016-11-16 - Assignees: The United States of America as represented by the Secretary of the Air Force - Applicants: The United States of America AS Represented By Te Secretary of the Air Force - Inventors: Kevin Kwiat; Charles Kamhoua; Laurent Njilla; Yiyu Shi; Travis Schulze - Web page: https://patentgrep.com/patent/US10121011B2 ## CPC - G10L 15/02: Feature extraction for speech recognition; Selection of recognition unit - G06F 21/32: using biometric data, e.g. fingerprints, iris scans or voiceprints - G06F 21/60: Protecting data - G06F 21/72: in cryptographic circuits - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G10L 25/84: for discriminating voice from noise - H04L 9/002: {Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441)} - H04L 45/02: Topology update or discovery - H04L 63/162: {at the data link layer} - G10L 15/16: using artificial neural networks - G10L 25/21: the extracted parameters being power information - G10L 25/24: the extracted parameters being the cepstrum - G10L 25/90: Pitch determination of speech signals - H04L 45/54: {Organization of routing tables} - H04L 2209/08: Randomization, e.g. dummy operations or using noise - H04L 2209/12: Details relating to cryptographic hardware or logic circuitry - G10L: SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Apparatus, method and article of manufacture providing a randomized encoding scheme for sequential logics, for resistance to data leakage. Invention employs dual-rail encoding to randomize the information in the chip, and employs three-dimensional integration technology to protect the critical information that is needed to decode the data anywhere on-chip. With the present invention, even when the entire design is completely known to the attacker who also has full access to the outsourced portion, it is still not always possible to identify the information in the chip using data leakage Trojans. ## Claims ### Claim 1 A sequential logic circuit security apparatus, comprising: at least two combinational logic circuit functions each having an output and at least one pair of logic inputs; at least two random logic state generators each randomly outputting a logic state 1 or 0; a first encoder for encoding each logic input of said at least one pair of logic inputs with a Boolean operation on a preselected one of said at least two random logic state generators; a multiplexer having an output, and at least two selectable inputs each being connected to a respective said output of said at least two combinational logic circuit functions, wherein said multiplexer selects one of said outputs of said at least two combinational logic circuit functions according to said logic state of said at least two random logic state generators; a latch having an input connected to said output of said multiplexer, an output, and a clock input; an exclusive OR circuit having an output, a first input connected to said latch output, and a second input, wherein said second input is encoded by a second encoder performing said Boolean operation on a current clock cycle state and a prior clock cycle state of said preselected one of said at least two random logic state generators. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein said Boolean operation is an exclusive OR operation. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein said second input is encoded by a second encoder performing said Boolean operation on: a current clock cycle state of a non-preselected one of said at least two random logic state generators; and a prior clock cycle state of said preselected one of said at least two random logic state generators. ### Claim 4 (depends on 2) The method of claim 2, wherein said Boolean operation is an exclusive OR operation. ### Claim 5 (depends on 4) The method of claim 4, wherein said second input is encoded by a step of performing said Boolean operation on: a current clock cycle state of a non-preselected one of said at least two random logic states; and a prior clock cycle state of said preselected one of said at least two random logic states. ### Claim 6 In a sequential logic circuit having at least two combinational logic circuit functions each having an output and at least one pair of logic inputs, a security method for use therewith, comprising the steps of: generating at least two random logic states each randomly comprising a logic state 1 or 0; encoding each logic input of said at least one pair of logic inputs with a Boolean operation on a preselected one of said at least two random logic states; selectively multiplexing said output of said at least two combinational logic circuit functions according to a logic state of said at least two random logic states; latching said multiplexed output of said at least two combinational logic circuit functions; exclusively OR'ing a first input comprising said multiplexed output of said at least two combinational logic circuit functions, with an encoded second input, wherein said second input is encoded by a step of performing said Boolean operation on a current clock cycle state and a prior clock cycle state of said preselected one of said at least two random logic states. ### Claim 7 A secure logic chip as an article of manufacture comprising a logic portion and a security portion, wherein said logic portion comprises a plurality of combinational logic circuits each having inputs and an output; said security portion comprises: a random logic state generator producing two randomly generated logic states; a multiplexer, having as inputs said outputs of said combinational logic circuits; and having a selection among said inputs based upon the logic state of said two randomly generated logic states; a latch for latching an output of said multiplexer; and an exclusive OR for decoding an output of said latch as a function of at least one of said two randomly generated logic states; and wherein said logic portion and said security portion are manufactured as separate chips and thereafter functionally integrated into said secure logic chip; and wherein said logic portion and said secure portion are functionally integrated by: arrangement as a physical stack; and through-silicon-vias to establish electrical connections between said logic portion and said secure portion. ### Claim 8 A semiconductor chip as an article of manufacture for securely encoding logic circuits, comprising: an array of security encoding cells fabricated onto said semiconductor chip, wherein each said cell further comprises: a multiplexer, having as inputs those outputs of said logic circuits to be securely encoded; and having a selection among said inputs based upon the logic state of one or more randomly generated logic states; a latch for latching an output of said multiplexer; and an exclusive OR for decoding an output of said latch as a function of said one or more randomly generated logic states; a crossbar structure for electrically interconnecting said one or more randomly generated logic states to all said security encoding cells in said semiconductor chip; and through-silicon-vias to establish electrical connections between said security encoding cells and said logic circuits.