# US 10,120,971 B2 · Integrated fan-out package and layout method thereof

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- Number: US 10,120,971 B2
- Document ID: US10120971B2
- Status: Granted
- Kind: B2
- Application number: 15/250,934
- Filed: 2016-08-30
- Published: 2018-03-01
- Granted: 2018-11-06
- Earliest claimed: 2016-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wan-Yu Lo; Chin-Chou Liu; Kuo-Nan Yang; Yu-Jen Chang
- Web page: https://patentgrep.com/patent/US10120971B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- G06F 2113/18: Chip packaging
- G06F 2119/10: Noise analysis or noise optimisation
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 70/656: Fan-in layouts
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

## Claims

### Claim 1

An integrated fan-out package, comprising:
a die having an interconnect structure therein; and
a fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof,
wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure,
wherein the fan-out substrate further has a plurality of second conductive bumps on the first surface thereof and aside the first conductive bumps, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, and
wherein the first and second conductive bumps are overlapped with each of the fan-out substrate and the die, and an underfill layer encapsulates the first and second conductive bumps.

### Claim 2 (depends on 1)

The integrated fan-out package of claim 1, wherein an aspect ratio of the first conductive bumps ranges from about 1/5 to 1/8.

### Claim 3 (depends on 1)

The integrated fan-out package of claim 1, wherein a width of the first conductive bumps is about 5 μm to 10 μm.

### Claim 4 (depends on 1)

The integrated fan-out package of claim 1, further comprising a dielectric layer encapsulating the first conductive bumps, wherein a dielectric constant of the dielectric layer is equal to or less than about 3.

### Claim 5 (depends on 1)

The integrated fan-out package of claim 1, wherein the interconnect layer comprises a plurality of first conductive lines, the conductive redistribution layer comprises a plurality of second conductive lines, and an area of a total of overlapped regions of the first and second conductive lines is less than a preset value determined by an integrated fan-out package performance according to capacitance and inductance information or a coupling effect between the die and the fan-out substrate.

### Claim 6 (depends on 1)

The integrated fan-out package of claim 1, wherein the interconnect layer comprises a plurality of first conductive lines, the conductive redistribution layer comprises a plurality of second conductive lines, and the first conductive lines are non-parallel to the second conductive lines.

### Claim 7 (depends on 1)

The integrated fan-out package of claim 1, wherein an aspect ratio of the second conductive bumps is the same as an aspect ratio of the first conductive bumps.

### Claim 8 (depends on 1)

The integrated fan-out package of claim 1, wherein an aspect ratio of the second conductive bumps is different from an aspect ratio of the first conductive bumps.

### Claim 9 (depends on 1)

The integrated fan-out package of claim 1, wherein an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

### Claim 10

An integrated fan-out package, comprising:
a die having an interconnect structure therein; and
a fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps and a plurality of second conductive bumps on a first surface thereof,
wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, and
wherein the interconnect layer of the interconnect structure comprises a plurality of first conductive lines, the conductive redistribution layer of the conductive redistribution layer structure comprises a plurality of second conductive lines, the first conductive lines of the die are, in a top view, non-parallel to the second conductive lines of the fan-out substrate, and in the top view, an area of a total of regions where the first conductive lines of the interconnect layer of the die are overlapped with the second conductive lines of the conductive redistribution layer of the fan-out substrate is smaller than a preset value determined by an integrated fan-out package performance according to capacitance and inductance information or a coupling effect between the die and the fan-out substrate, wherein the plurality of first conductive bumps and the plurality of second conductive bumps are overlapped with each of the fan-out substrate and the die.

### Claim 11 (depends on 10)

The integrated fan-out package of claim 10, further comprising a dielectric layer encapsulating the first conductive bumps, wherein a dielectric constant of the dielectric layer is equal to or less than about 3.

### Claim 12 (depends on 10)

The integrated fan-out package of claim 10, wherein an aspect ratio of the second conductive bumps is the same as the aspect ratio of the first conductive bumps.

### Claim 13 (depends on 10)

The integrated fan-out package of claim 10, wherein an aspect ratio of the second conductive bumps is different from the aspect ratio of the first conductive bumps.

### Claim 14

An integrated fan-out package, comprising:
a die having an interconnect structure therein; and
a fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps and a plurality of second conductive bumps on a first surface thereof,
wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, and
wherein the interconnect layer of the interconnect structure comprises a plurality of first conductive lines, the conductive redistribution layer of the conductive redistribution layer structure comprises a plurality of second conductive lines, at least some of the first conductive lines of the die are, in a top view, parallel to the second conductive lines of the fan-out substrate, and in the top view, an area of a total of regions where the first conductive lines of the interconnect layer of the die are overlapped with the second conductive lines of the conductive redistribution layer of the fan-out substrate is smaller than a preset value determined by an integrated fan-out package performance according to capacitance and inductance information or a coupling effect between the die and the fan-out substrate, wherein the plurality of first conductive bumps and the plurality of second conductive bumps are overlapped with each of the fan-out substrate and the die.

### Claim 15 (depends on 14)

The integrated fan-out package of claim 14, further comprising a dielectric layer encapsulating the first conductive bumps, wherein a dielectric constant of the dielectric layer is equal to or less than about 3.

### Claim 16 (depends on 14)

The integrated fan-out package of claim 14, wherein an aspect ratio of the second conductive bumps is the same as the aspect ratio of the first conductive bumps.

### Claim 17 (depends on 14)

The integrated fan-out package of claim 14, wherein an aspect ratio of the second conductive bumps is different from the aspect ratio of the first conductive bumps.