# US 10,120,831 B1 · Circuit and method for handling write and read requests between a master circuit and a slave circuit in different clock domains > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,831 B1 - Document ID: US10120831B1 - Status: Granted - Kind: B1 - Application number: 15/367,611 - Filed: 2016-12-02 - Granted: 2018-11-06 - Earliest claimed: 2016-12-02 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Mahesh Sankroj; Jason Villarreal - Web page: https://patentgrep.com/patent/US10120831B1 ## CPC - G06F 13/4291: {using a clocked protocol} - G06F 13/1673: {using buffers} - G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines - G06F 13/404: {with address mapping} - G06F 13/405: {where the bridge performs a synchronising function} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A circuit arrangement for handling write and read requests between a master circuit and a slave circuit in different clock domains includes first and second write FIFO circuits, a read FIFO circuit, and a write acknowledgment circuit. The first write FIFO circuit is configured and arranged to receive and buffer write addresses of write requests received from a master circuit and addressed to a slave circuit. The second write FIFO circuit is configured and arranged to receive and buffer write data associated with the write addresses of the write requests. The read FIFO circuit is configured and arranged to receive and buffer read addresses of read requests received from the master circuit and addressed to the slave circuit. The write acknowledgment control circuit is configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request. ## Claims ### Claim 1 A circuit arrangement comprising: a first write FIFO circuit configured and arranged to receive and buffer write addresses of write requests from a master circuit and addressed to a slave circuit, wherein the first write FIFO circuit has a write port clocked by a first clock signal and a read port clocked by a second clock signal; a second write FIFO circuit configured and arranged to receive and buffer write data associated with the write addresses of the write requests, wherein the second write FIFO circuit has a write port clocked by the first clock signal and a read port clocked by the second clock signal; a read FIFO circuit configured and arranged to receive and buffer read addresses of read requests from the master circuit and addressed to the slave circuit; and a write acknowledgement control circuit configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request, wherein the write acknowledgement control circuit is further configured and arranged to transmit an acknowledgement to a write address received when the second clock signal is running and to transmit an acknowledgement to a write address received when the second clock signal is stopped. ### Claim 2 (depends on 1) The circuit arrangement of claim 1, wherein the first clock signal has signal attributes different from signal attributes of the second clock signal. ### Claim 3 (depends on 1) The circuit arrangement of claim 1, wherein the first clock signal and the second clock signal have different clock frequencies. ### Claim 4 (depends on 1) The circuit arrangement of claim 1, wherein the first clock signal is faster and the second clock signal have different phases. ### Claim 5 (depends on 1) The circuit arrangement of claim 1, wherein the write acknowledgement control circuit is further configured and arranged to transmit an acknowledgement to a write address received when the second clock signal is running at a first rate and to transmit an acknowledgement to a write address received when the second clock signal is running at a second rate that is less than the first rate. ### Claim 6 (depends on 1) The circuit arrangement of claim 1, wherein the write acknowledgement control circuit is further configured and arranged to: transmit an acknowledgement to a write address received when the second clock signal is running at a first rate; transmit an acknowledgement to a write address received when the second clock signal is stopped; and transmit an acknowledgement to a write address received when the second clock signal is running at a second rate that is less than the first rate. ### Claim 7 (depends on 1) The circuit arrangement of claim 1, further comprising a read acknowledgement control circuit configured and arranged to transmit an acknowledgement to a read address to the master circuit before the slave circuit responds to the read address. ### Claim 8 (depends on 1) The circuit arrangement of claim 1, wherein: the first clock signal has signal attributes different from signal attributes of the second clock signal; and the circuit arrangement further includes an acknowledgement analyzer circuit configured and arranged to: receive responses from the slave circuit; and re-transmit a write address from the first write FIFO circuit and corresponding write data from the second write FIFO circuit to the slave circuit in response to the second clock signal running and the acknowledgement analyzer circuit not receiving a response from the slave circuit for a previous transmission of the write address and the corresponding write data to the slave circuit. ### Claim 9 (depends on 1) The circuit arrangement of claim 1, wherein: the first clock signal has signal attributes different from signal attributes of the second clock signal; and the circuit arrangement further includes a clock monitor circuit configured and arranged to: monitor the second clock signal; and generate an interrupt signal to the master circuit in response to detecting that the second clock signal stopped. ### Claim 10 A circuit arrangement, comprising: a master circuit configured and arranged to issue write requests and read requests; a slave circuit configured and arranged to process the write requests and read requests; and a transaction adapter coupling the master circuit to the slave circuit, wherein the transaction adapter includes: a first write FIFO circuit configured and arranged to receive and buffer write addresses of the write requests from the master circuit and addressed to the slave circuit, wherein the first write FIFO circuit has a write port clocked by a first clock signal and a read port clocked by a second clock signal; a second write FIFO circuit configured and arranged to receive and buffer write data associated with the write addresses of the write requests, wherein the second write FIFO circuit has a write port clocked by the first clock signal and a read port clocked by the second clock signal; a read FIFO circuit configured and arranged to receive and buffer read addresses of the read requests from the master circuit and addressed to the slave circuit; and a write acknowledgement control circuit configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request, wherein the write acknowledgement control circuit is further configured and arranged to transmit an acknowledgement to a write address received when the second clock signal is running at a first rate, and transmit an acknowledgement to a write address received when the second clock signal is stopped. ### Claim 11 (depends on 10) The circuit arrangement of claim 10, wherein the first clock signal has signal attributes different from signal attributes of the second clock signal. ### Claim 12 (depends on 10) The circuit arrangement of claim 10, wherein the first clock signal and the second clock signal have different clock frequencies. ### Claim 13 (depends on 10) The circuit arrangement of claim 10, wherein the first clock signal is faster and the second clock signal have different phases. ### Claim 14 (depends on 13) The circuit arrangement of claim 13, wherein the write acknowledgement control circuit is further configured and arranged to transmit an acknowledgement to a write address received when the second clock signal is running at a second rate that is less than the first rate. ### Claim 15 A method of processing requests from a master circuit to a slave circuit, comprising: storing in a first write FIFO circuit of a transaction adapter, write addresses of write requests from the master circuit and addressed to the slave circuit; inputting a first clock signal to a write port of the first write FIFO circuit and inputting a second clock signal to a read port of the first write FIFO circuit, wherein the first clock signal has signal attributes different from signal attributes of the second clock signal; storing in a second write FIFO circuit of the transaction adapter, write data associated with the write addresses of the write requests; inputting the first clock signal to a write port of the second write FIFO circuit and inputting the second clock signal to a read port of the second write FIFO circuit; storing in a read FIFO circuit of the transaction adapter, read addresses of read requests from the master circuit and addressed to the slave circuit; transmitting by the transaction adapter, an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request; transmitting an acknowledgement to a write address received when the second clock signal is running at a first rate; transmitting an acknowledgement to a write address received when the second clock signal is stopped. ### Claim 16 (depends on 15) The method of claim 15, wherein the first clock signal has signal attributes different from signal attributes of the second clock signal. ### Claim 17 (depends on 15) The method of claim 15, wherein the first clock signal and the second clock signal have different clock frequencies. ### Claim 18 (depends on 15) The method of claim 15, wherein the first clock signal is faster and the second clock signal have different phases. ### Claim 19 (depends on 15) The method of claim 15, further comprising transmitting an acknowledgement to a write address received when the second clock signal is running at a second rate that is less than the first rate.