# US 10,120,826 B2 · Single-chip control module for an integrated system-on-a-chip for silicon photonics > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,826 B2 - Document ID: US10120826B2 - Status: Granted - Kind: B2 - Application number: 15/810,556 - Filed: 2017-11-13 - Published: 2018-03-08 - Granted: 2018-11-06 - Earliest claimed: 2013-07-02 - Assignees: Inphi Corporation - Applicants: Inphi Corporation - Inventors: Siddharth Sheth; Radhakrishnan L. Nagarajan - Web page: https://patentgrep.com/patent/US10120826B2 ## CPC - G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation - G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines - G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 15/7817: {Specially adapted for signal processing, e.g. Harvard architectures} - H04L 1/0041: {Arrangements at the transmitter end} - H04L 25/03006: {Arrangements for removing intersymbol interference} - H04L 25/49: using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} - H04L 1/0003: {by switching between different modulation schemes} - H04L 27/34: Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems - H04L 2001/0094: {Bus} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device. ## Claims ### Claim 1 An integrated single-chip control device for a system-on-a-chip in a communication network, the integrated single-chip control device comprising: a silicon substrate member; a data input/output interface provided on the silicon substrate member and configured for a predefined data rate and protocol; an input/output block provided on the silicon substrate member and coupled to the data input/output interface, the input/output block comprising a receiving block and a transmitting block for respectively receiving and transmitting data signals up to 8 lanes with a first rate from and to a very-short-reach (VSR) network host; an auto-negotiation block configured to negotiate link operational mode between the network host and the input/output block; a signal processing block provided on the silicon substrate member and coupled to the input/output block using a bi-direction bus in an intermediary protocol; a driver module provided on the silicon substrate member and coupled to the signal processing block using a crossbar switch; a driver interface provided on the silicon substrate member and coupled to the driver module and configured to couple to a silicon photonics device, the driver interface being configured to transmit output data up to 8 lanes in an amplitude modulation format with a second data rate; a receiver module provided on the silicon substrate member and configured to couple to the silicon photonics device using predefined modulation format to receive information converted from optical signals and couple to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface; a communication block provided on the silicon substrate member and operably coupled to the input/output block, the signal processing block, the driver module, and the receiver module for multiple series communications; and a communication interface coupled to the communication block. ### Claim 2 (depends on 1) The integrated single-chip control device of claim 1 wherein the driver module is selected from a current drive or a voltage driver. ### Claim 3 (depends on 1) The integrated single-chip control device of claim 1 wherein the driver module is a differential driver. ### Claim 4 (depends on 1) The integrated single-chip control device of claim 1 wherein the amplitude modulation format is selected from NRZ format or PAM-4 format. ### Claim 5 (depends on 1) The integrated single-chip control device of claim 1 wherein the data input/output interface is configured to receive/send electrical signals from/to the VSR host up to eight lanes with the first data rate of 50 Gbps in PAM-4 format or 25 Gbps in NRZ format. ### Claim 6 (depends on 1) The integrated single-chip control device of claim 1 wherein the driver interface is configured to transmit output data up to 8 lanes with the second data rate the same as the first rate in PAM-4 format. ### Claim 7 (depends on 1) The integrated single-chip control device of claim 1 wherein the driver module and the receiver module comprise a Chip-to-Backplane Ethernet KR physical link for coupling with the silicon photonics device. ### Claim 8 (depends on 1) The integrated single-chip control device of claim 1 wherein the silicon photonic device is configured to convert the output data into an output transport data in a WDM optical signal with an amplitude modulation format. ### Claim 9 (depends on 1) The integrated single-chip control device of claim 1 wherein the driver module is configured to couple with a control block for initiating control of a laser bias or a modulator bias for the silicon photonics device. ### Claim 10 (depends on 9) The integrated single-chip control device of claim 9 wherein the control block is configured to drive a thermal tuning or carrier tuning device each of which is configured on the silicon photonics device. ### Claim 11 (depends on 1) The integrated single-chip control device of claim 1 wherein the receiver module is configured to convert optical signals from the silicon photonics device to electrical current signals. ### Claim 12 (depends on 1) The integrated single-chip control device of claim 1 wherein the signal processing block comprises a first digital logic block including a cross-point switch coupled to the receiving block and the driver module, and a second digital logic block including a cross-point switch coupled to the transmitting block and the receiver module. ### Claim 13 (depends on 12) The integrated single-chip control device of claim 12 wherein the signal processing block is characterized by high performance in >30 dB DFE/FFE/CLTE optimized equalization for both signal transmission and receiving. ### Claim 14 (depends on 1) The integrated single-chip control device of claim 1 wherein the first digital logic block and the second digital logic block comprise a SerDes block configured to convert data streams of N into data streams of M and a forward error correction (FEC) block with variable rate in 200/100/50/40/25/10 Gbps. ### Claim 15 (depends on 1) The integrated single-chip control device of claim 1 wherein the communication block comprises a multi-point control unit (MCU) and a phase-locked loop (PLL) with a reference clock input. ### Claim 16 (depends on 1) The integrated single-chip control device of claim 1 wherein the communication interface comprises a Management Data Input/Output interface or an I2C-type interface. ### Claim 17 (depends on 15) The integrated single-chip control device of claim 15 wherein the communication block further comprises a test/diagnostics unit including a general purpose Input/Output port for communicating host and line loopbacks, a Scan port for supporting Eye-Scan/Histograms, and a test access port with JTAG interface. ### Claim 18 (depends on 15) The integrated single-chip control device of claim 15 wherein the communication block further comprises a power supply module configured to receive power supplies of 0.8 V and 1.125 V. ### Claim 19 A method of using an integrated single-chip control device in a system-on-a-chip configured in a communication network, the method comprising: providing a host photonics device in a first die, the host photonics device comprising at least a laser device, a modulator, a photo detector, and an optical mux/demux device; providing an integrated single-chip control device in a second die, the integrated single-chip control device comprising: a silicon substrate member; a data input/output interface provided on the silicon substrate member and configured for a predefined data rate and protocol; an input/output block provided on the silicon substrate member and coupled to the data input/output interface, the input/output block comprising a receiving block and a transmitting block for respectively receiving and transmitting data signals up to 8 lanes with a first rate from and to a very-short-reach (VSR) network host; an auto-negotiation block configured to negotiate link operational mode between the network host and the input/output block; a signal processing block provided on the silicon substrate member and coupled to the input/output block using a bi-direction bus in an intermediary protocol; a driver module provided on the silicon substrate member and coupled to the signal processing block using a crossbar switch; a driver interface provided on the silicon substrate member and coupled to the driver module and configured to couple to a silicon photonics device, the driver interface being configured to transmit output data up to 8 lanes in an amplitude modulation format with a second data rate; a receiver module provided on the silicon substrate member, and configured to couple to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface; a communication block provided on the silicon substrate member and operably coupled to the input/output block, the signal processing block, the driver module, and the receiver module for multiple series communications; and a communication interface coupled to the communication block; connecting the host photonics device in the first die to the integrated single-chip control device in the second die via a switch; connecting the integrated single-chip control device in the second die to Back Plane via a KR physical link; and transferring signals from the integrated single-chip control device to the host photonics device via the Back Plane. ### Claim 20 A network system comprising an integrated single-chip control device coupled with a host photonics device for controlling optoelectronic signals communication in a network, the integrated single-chip control device comprising: a silicon substrate member; a data input/output interface provided on the silicon substrate member and configured for a predefined data rate and protocol; an input/output block provided on the silicon substrate member and coupled to the data input/output interface, the input/output block comprising a receiving block and a transmitting block for respectively receiving and transmitting data signals up to 8 lanes with a first rate from and to a very-short-reach (VSR) network host; an auto-negotiation block configured to negotiate link operational mode between the network host and the input/output block; a signal processing block provided on the silicon substrate member and coupled to the input/output block using a bi-direction bus in an intermediary protocol; a driver module provided on the silicon substrate member and coupled to the signal processing block using a crossbar switch; a driver interface provided on the silicon substrate member and coupled to the driver module and configured to be coupled to the silicon photonics device, the driver interface being configured to transmit output data up to 8 lanes in an amplitude modulation format with a second data rate; a receiver module provided on the silicon substrate member and configured to couple to the silicon photonics device using predefined modulation format to receive information converted from optical signals and couple to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface; a communication block provided on the silicon substrate member and operably coupled to the input/output block, the signal processing block, the driver module, and the receiver module for multiple series communications; and a communication interface coupled to the communication block; the host photonics device comprising at least a laser device, a modulator, a photo detector, and an optical mux/demux device, the host photonics device being formed in a separate die coupled to the integrated single-chip control device via a switch.