# US 10,120,810 B2 · Implementing selective cache injection

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- Number: US 10,120,810 B2
- Document ID: US10120810B2
- Status: Granted
- Kind: B2
- Application number: 15/829,032
- Filed: 2017-12-01
- Published: 2018-03-29
- Granted: 2018-11-06
- Earliest claimed: 2013-07-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Philip Heidelberger; Hillery C. Hunter; James A. Kahle; Ravi Nair
- Web page: https://patentgrep.com/patent/US10120810B2

## CPC

- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 2212/1024: Latency reduction
- G06F 2212/154: Networked environment
- G06F 2212/604: Details relating to cache allocation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

## Claims

### Claim 1

A method for implementing memory hierarchy placement decisions in a memory system in a computer system comprising:
providing a memory controller in the memory system;
providing an in-memory processing element in the memory system;
receiving first data from an input output (IO) device and receiving second data exchanged over a network;
routing arriving first data and second data directly into the memory system;
selectively injecting the first data and the second data into a processor cache; and
using one of said memory controller and said in-memory processing element in the memory system, selectively driving data placement into a level of the memory hierarchy based upon the arrival of first data from said input output (IO) device, and from one of computation and a directive of said in-memory processing element.

### Claim 2 (depends on 1)

The method as recited in claim 1 wherein selectively injecting the data into the processor cache includes using the memory controller including the in-memory processing element in the memory system to determine data routing.

### Claim 3 (depends on 1)

The method as recited in claim 1 includes holding the injected data in the processor cache until accessed or deallocated by a processor.

### Claim 4 (depends on 1)

The method as recited in claim 1 wherein selectively injecting the data into the processor cache includes providing directory bits with the injected cache data to prevent premature eviction.

### Claim 5 (depends on 4)

The method as recited in claim 4 includes clearing the directory bits when the injected cache data is accessed and deallocated by a processor.

### Claim 6 (depends on 1)

The method as recited in claim 1 wherein selectively driving data placement into a level of the memory hierarchy includes rerouting changed data into the processor cache.

### Claim 7 (depends on 1)

The method as recited in claim 1 wherein selectively injecting the data into the processor cache includes performing at least one predefined operation and creating changed data for injecting the changed data into the processor cache.