# US 10,120,808 B2 · Apparatus having cache memory disposed in a memory transaction path between interconnect circuitry and a non-volatile memory, and corresponding method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,808 B2 - Document ID: US10120808B2 - Status: Granted - Kind: B2 - Application number: 15/135,916 - Filed: 2016-04-22 - Published: 2017-10-26 - Granted: 2018-11-06 - Earliest claimed: 2016-04-22 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Gergely Kiss; Gábor Móricz; Man Cheung Joseph Yiu - Web page: https://patentgrep.com/patent/US10120808B2 ## CPC - G06F 12/0879: Burst mode - G06F 11/36: Prevention of errors by analysis, debugging or testing of software - G06F 12/0862: with prefetch - G06F 12/0888: using selective caching, e.g. bypass - G06F 12/0893: Caches characterised by their organisation or structure - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 2212/222: Non-volatile memory - G06F 2212/6028: Prefetching based on hints or prefetch instructions - G06F 2212/6032: Way prediction in set-associative cache - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing system includes interconnect circuitry providing a plurality of memory transaction paths between one or more transaction masters, including a processor, debugging circuitry and a DMA unit, and one or more transaction slaves including a non-volatile memory, a DRAM memory and an I/O interface. A cache memory is provided between the interconnect circuitry and the non-volatile memory. This cache memory may be a two way set associative cache memory. The cache memory may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory upon the cache miss. ## Claims ### Claim 1 Apparatus for processing data, comprising: interconnect circuitry to provide a plurality of memory transaction paths between one or more transaction masters and one or more transaction slaves; wherein: said one or more transaction slaves comprise a non-volatile memory to store data, and said one or more transaction masters comprise a processor to perform processing operations at least partially specified by program instructions stored in said non-volatile memory; and further comprising a cache memory disposed in a memory transaction path between said interconnect circuitry and said non-volatile memory to cache data read from said non-volatile memory, wherein: said cache memory is responsive to a non-cacheable signal accompanying a memory transaction and identifying that said memory transaction is a non-cacheable transaction to non-cacheable data to bypass operation of said cache memory in servicing said non-cacheable transaction. ### Claim 2 (depends on 1) The apparatus as claimed in claim 1, wherein said cache memory is a read-only cache memory. ### Claim 3 (depends on 1) The apparatus as claimed in claim 1, wherein said cache memory is an associative cache memory. ### Claim 4 (depends on 3) The apparatus as claimed in claim 3, wherein said associative cache memory is two way set associative. ### Claim 5 (depends on 1) The apparatus as claimed in claim 1, wherein said interconnect circuitry provides a memory transaction path to transfer N bits of data in parallel between said processor and said cache memory. ### Claim 6 (depends on 1) The apparatus as claimed in claim 1, wherein said program instructions comprise at least one of N-bit program instructions and N/2-bit program instructions. ### Claim 7 (depends on 5) The apparatus as claimed in claim 5, wherein said cache memory is coupled to said non-volatile memory via a cache interface to transfer in parallel M*N bits of data from said non-volatile memory to said cache memory, and M is an integer greater than one. ### Claim 8 (depends on 7) The apparatus as claimed in claim 7, wherein said cache memory comprises a plurality of cache lines each storing M*N bits of data. ### Claim 9 (depends on 1) The apparatus as claimed in claim 1, wherein said cache memory comprises a plurality of cache lines and is responsive to a cache miss corresponding to a memory transaction attempting to read target data from said cache memory to perform a cache fill operation to load a cache line of said plurality of cache lines with data including said target data. ### Claim 10 (depends on 9) The apparatus as claimed in claim 9, wherein said cache memory is responsive to an instruction-fetch signal accompanying said memory transaction and identifying that said memory transaction is an instruction-read transaction attempting to read a program instruction to perform a prefetch cache fill operation to load at least one further cache line of said plurality of cache lines with data from said non-volatile memory contiguous with and following in a memory address space of said non-volatile memory said cache line of data including said target data. ### Claim 11 (depends on 10) The apparatus as claimed in claim 10, wherein said cache memory is responsive to a software controlled parameter to disable said prefetch cache fill operation of said cache memory. ### Claim 12 (depends on 1) The apparatus as claimed in claim 1, wherein said plurality of transaction masters include debugging circuitry, said cache memory is responsive to a debug signal accompanying a memory transaction and identifying that said memory transaction is a debug transaction issued by said debugging circuit to bypass operation of said cache memory in servicing said debug transaction. ### Claim 13 (depends on 7) The apparatus as claimed in claim 7, wherein said one or more transaction masters comprise a processor to perform processing operations at least partially specified by program instructions stored in said non-volatile memory and said processor executes said program instructions at a maximum rate of X Hertz and said non-volatile memory supports said transfer of said M*N bits of program instruction data to said cache memory at rate of at least X/M Hertz. ### Claim 14 (depends on 1) The apparatus as claimed in claim 1, comprising a plurality of transaction slaves mapped to different regions within a memory address space. ### Claim 15 (depends on 1) The apparatus as claimed in claim 1, wherein said non-volatile memory is an execute-in-place memory. ### Claim 16 (depends on 1) The apparatus as claimed in claim 1, wherein said non-volatile memory is one of: eFlash memory, mask ROM, PROM, EPROM, EEPROM, nvSRAM, FeRAM, PRAM, CBRAM, NRAM, RRAM, and FJGRAM. ### Claim 17 Apparatus for processing data comprising: means for providing a plurality of memory transaction paths between one or more transaction masters and one or more transaction slaves; wherein: said one or more transaction slaves comprise means for storing data, and said one or more transaction masters comprise a processor to perform processing operations at least partially specified by program instructions stored in said non-volatile memory; and further comprising: means, disposed in a memory transaction path between said means for providing and said means for storing data, for caching data read from said means for storing data, wherein: said means for caching data is responsive to a non-cacheable signal accompanying a memory transaction and identifying that said memory transaction is a non-cacheable transaction to non-cacheable data to bypass operation of said means for caching data in servicing said non-cacheable transaction. ### Claim 18 A method of processing data, comprising: providing a plurality of memory transaction paths via interconnect circuitry between one or more transaction masters and one or more transaction slaves; wherein: said one or more transaction slaves comprise a non-volatile memory to store data, and said one or more transaction masters comprise a processor to perform processing operations at least partially specified by program instructions stored in said non-volatile memory; and further comprising caching data read from said non-volatile memory in a cache memory disposed in a memory transaction path between said interconnect circuitry and said non-volatile memory, wherein: said cache memory is responsive to a non-cacheable signal accompanying a memory transaction and identifying that said memory transaction is a non-cacheable transaction to non-cacheable data to bypass operation of said cache memory in servicing said non-cacheable transaction.