# US 10,120,806 B2 · Multi-level system memory with near memory scrubbing based on predicted far memory idle time > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,806 B2 - Document ID: US10120806B2 - Status: Granted - Kind: B2 - Application number: 15/193,952 - Filed: 2016-06-27 - Published: 2017-12-28 - Granted: 2018-11-06 - Earliest claimed: 2016-06-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Zhe Wang; Christopher B. Wilkerson; Zeshan A. Chishti - Web page: https://patentgrep.com/patent/US10120806B2 ## CPC - G06F 12/0873: Mapping of cache memory to specific storage devices or parts thereof - G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list - G06F 12/124: {being minimized, e.g. non MRU} - G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning - G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 2212/1021: Hit rate improvement - G06F 2212/283: Plural cache memories - G06F 2212/313: In storage device - G06F 2212/608: Details relating to cache mapping - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory. ## Claims ### Claim 1 An apparatus, comprising: a memory controller to interface to a multi-level system memory, the memory controller comprising least recently (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory, the memory controller comprising idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory, the memory controller to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that a currently observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory. ### Claim 2 (depends on 1) The apparatus of claim 1 wherein the higher level of the multi-level system memory comprises a memory side cache for the lower level of the multi-level system memory. ### Claim 3 (depends on 2) The apparatus of claim 2 wherein the one or more lesser used cache lines are dirty cache lines. ### Claim 4 (depends on 1) The apparatus of claim 1 wherein the one or more cache lesser used cache lines are selectable from more than one position of an LRU queue that is implemented with the LRU circuitry. ### Claim 5 (depends on 4) The apparatus of claim 4 wherein the more than one position is limited to one or more lower positions of the LRU queue so as not to select cache lines for scrubbing to the lower level of the multi-level system memory that have a likelihood of experiencing a cache hit, where, the higher level of the multi-level system memory is a memory side cache for the lower level of the multi-level system memory. ### Claim 6 (depends on 4) The apparatus of claim 4 wherein different positions of the more than one LRU position have different expected idle time thresholds to trigger a scrub of their constituent cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory. ### Claim 7 (depends on 4) The apparatus of claim 4 wherein different positions of the more than one LRU position have respective counters to count how many cache line in a particular LRU position are dirty. ### Claim 8 A computing system, comprising: one or more processing cores; a networking interface; a multi-level system memory; a memory controller to interface to the multi-level system memory, the memory controller comprising least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory, the memory controller comprising idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory, the memory controller to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that a currently observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory. ### Claim 9 (depends on 8) The computing system of claim 8 wherein the higher level of the multi-level system memory comprises a memory side cache for the lower level of the multi-level system memory. ### Claim 10 (depends on 9) The computing system of claim 9 wherein the one or more lesser used cache lines are dirty cache lines. ### Claim 11 (depends on 8) The computing system of claim 8 wherein the one or more cache lesser used cache lines are selectable from more than one position of an LRU queue that is implemented with the LRU circuitry. ### Claim 12 (depends on 11) The computing system of claim 11 wherein the more than one position is limited to one or more lower positions of the LRU queue so as not to select cache lines for scrubbing to the lower level of the multi-level system memory that have a likelihood of experiencing a cache hit, where, the higher level of the multi-level system memory is a memory side cache for the lower level of the multi-level system memory. ### Claim 13 (depends on 11) The computing system of claim 11 wherein different positions of the more than one LRU position have different expected idle time thresholds to trigger a scrub of their constituent cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory. ### Claim 14 (depends on 11) The computing system of claim 11 wherein different positions of the more than one LRU position have respective counters to count how many cache line in a particular LRU position are dirty. ### Claim 15 A method, comprising: tracking least recently used cache lines in a memory side cache of a multi-level system memory; predicting a time length of a currently observed idle time in a lower level of the multi-level system memory that the memory side cache acts as a cache for; and, writing one or more of the least recently used cache lines from the memory side cache into the lower level of the multi-level system memory in response to the time length being deemed sufficiently long to accommodate the writing of the one or more of the least recently used cache lines from the memory side cache into the lower level of the multi-level system memory. ### Claim 16 (depends on 15) The method of claim 15 wherein the one or more cache lines are dirty cache lines. ### Claim 17 (depends on 15) The method of claim 15 wherein the time length is deemed long enough to select cache lines from more than one position of a least recently used queue that is used to perform the tracking of the least recently used cache lines. ### Claim 18 (depends on 17) The method of claim 17 wherein the more than one position is limited to lowest positions in the least recently used queue so that cache lines that are likely to experience a cache hit in the memory side cache are not written back to the lower level of the multi-level system memory.