# US 10,120,805 B2 · Managing memory for secure enclaves

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- Number: US 10,120,805 B2
- Document ID: US10120805B2
- Status: Granted
- Kind: B2
- Application number: 15/408,774
- Filed: 2017-01-18
- Published: 2018-07-19
- Granted: 2018-11-06
- Earliest claimed: 2017-01-18
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Rebekah M. Leslie-Hurd; Francis X. McKeen; Carlos V. Rozas; Gilbert Neiger; Asit Mallick; Ittai Anati; Ilya Alexandrovich; Vedvyas Shanbhogue; Somnath Chakrabarti
- Web page: https://patentgrep.com/patent/US10120805B2

## CPC

- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP}
- G06F 12/1441: {for a range}
- G06F 12/1475: {in a virtual system, e.g. with translation means}
- G06F 2009/45583: {Memory management, e.g. access or allocation}
- G06F 2009/45591: {Monitoring or debugging support}
- G06F 2212/152: Virtualized environment, e.g. logically partitioned system
- G06F 2212/60: Details of cache memory
- G06F 2212/68: Details of translation look-aside buffer [TLB]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.

## Claims

### Claim 1

A processing device comprising:
a conflict resolution logic circuit to:
initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave;
execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction; and
determine that a tracking instruction error is generated by the tracking instruction, wherein the tracking instruction error is encountered by a guest operating system (OS) of a virtual machine (VM).

### Claim 2 (depends on 1)

The processing device of claim 1 wherein the tracking instruction is executed for a parent page and corresponding child pages of the parent page for each of a plurality of EPC pages in the enclave.

### Claim 3 (depends on 1)

The processing device of claim 1 wherein the tracking instruction error is encountered by a guest operating system (OS) of a virtual machine (VM) managed by a virtual machine monitor (VMM), wherein the tracking instruction error is encountered upon a conflict occurring during the tracking phase between the VMM and the guest OS that both execute the tracking instruction to monitor the EPC page, wherein the VM is unaware of the conflict.

### Claim 4 (depends on 3)

The processing device of claim 3 wherein the conflict resolution logic circuit is further to trigger a conflict execution control VM exit in response to the conflict occurring during the tracking phase between the VMM and the guest OS that both execute the tracking instruction to monitor the EPC page, wherein the conflict execution control VM exit allows the VMM to resolve the conflict such that the VM is unaware of the VMM resolving the conflict.

### Claim 5 (depends on 4)

The processing device of claim 4 wherein the conflict resolution logic circuit is further to receive control of execution of the VM in response to the triggering of the conflict execution control VM exit.

### Claim 6 (depends on 5)

The processing device of claim 5 wherein responsive to the VMM receiving control of execution of the VM, the VMM is to pause a paging thread of the VMM that is working on the secure enclave.

### Claim 7 (depends on 6)

The processing device of claim 6 wherein the VMM is further to redirect the paging thread to work on a second secure enclave, wherein the second secure enclave is different from the secure enclave.

### Claim 8 (depends on 6)

The processing device of claim 6 wherein, subsequent to pausing the paging thread, the VMM to reenter the VM at an instruction pointer that a return instruction pointer (RIP) pointed to when the conflict execution control VM exit was taken.

### Claim 9

A system comprising:
a memory; and
a conflict resolution logic circuit coupled to the memory to:
initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave;
execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction; and
determine that a tracking instruction error is generated by the tracking instruction, wherein the tracking instruction error is encountered by a guest operating system (OS) of a virtual machine (VM).

### Claim 10 (depends on 9)

The system of claim 9 wherein the tracking instruction error is encountered by a guest operating system (OS) of a virtual machine (VM) managed by a virtual machine monitor (VMM), wherein the tracking instruction error is encountered upon a conflict occurring during the tracking phase between the VMM and the guest OS that both execute the tracking instruction to monitor the EPC page, wherein the VM is unaware of the conflict.

### Claim 11 (depends on 10)

The system of claim 10 wherein the conflict resolution logic circuit is further to trigger a conflict execution control VM exit in response to the conflict occurring during the tracking phase between the VMM and the guest OS that both execute the tracking instruction to monitor the EPC page, wherein the conflict execution control VM exit allows the VMM to resolve the conflict such that the VM is unaware of the VMM resolving the conflict.

### Claim 12 (depends on 11)

The system of claim 11 wherein the conflict resolution logic circuit is further to receive control of execution of the VM in response to the triggering of the conflict execution control VM exit, and wherein responsive to the VMM receiving control of execution of the VM, the VMM is to pause a paging thread of the VMM that is working on the secure enclave.

### Claim 13

A non-transitory machine-readable storage medium including instructions that, when accessed by a processing device, cause the processing device to perform operations comprising:
initiating, by a processing device, a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave; and
executing, by the processing device, a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction; and
determining that a tracking instruction error is generated by the tracking instruction, wherein the tracking instruction error is encountered by a guest operating system (OS) of a virtual machine (VM).

### Claim 14 (depends on 13)

The non-transitory machine-readable storage medium of claim 13 wherein the tracking instruction error is encountered by a guest operating system (OS) of a virtual machine (VM) managed by a virtual machine monitor (VMM), wherein the tracking instruction error is encountered upon a conflict occurring during the tracking phase between the VMM and the guest OS that both execute the tracking instruction to monitor the EPC page, wherein the VM is unaware of the conflict.

### Claim 15 (depends on 14)

The non-transitory machine-readable storage medium of claim 14 further comprising triggering a conflict execution control VM exit in response to the conflict occurring during the tracking phase between the VMM and the guest OS that both execute the tracking instruction to monitor the EPC page, wherein the conflict execution control VM exit allows the VMM to resolve the conflict such that the VM is unaware of the VMM resolving the conflict.

### Claim 16 (depends on 15)

The non-transitory machine-readable storage medium of claim 15 further comprising receiving control of execution of the VM in response to the triggering of the conflict execution control VM exit, wherein responsive to the VMM receiving control of execution of the VM, the VMM is to pause a paging thread of the VMM that is working on the secure enclave.

### Claim 17 (depends on 16)

The non-transitory machine-readable storage medium of claim 16 wherein, subsequent to pausing the paging thread, the VMM to reenter the VM at an instruction pointer that a return instruction pointer (RIP) pointed to when the conflict execution control VM exit was taken.