# US 10,120,803 B2 · Transactional memory coherence control

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- Number: US 10,120,803 B2
- Document ID: US10120803B2
- Status: Granted
- Kind: B2
- Application number: 14/931,912
- Filed: 2015-11-04
- Published: 2017-03-23
- Granted: 2018-11-06
- Earliest claimed: 2015-09-23
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Fadi Y. Busaba; Harold W. Cain, III; Michael Karl Gschwind; Valentina Salapura; Eric M. Schwarz; Timothy J. Slegel
- Web page: https://patentgrep.com/patent/US10120803B2

## CPC

- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 9/467: {Transactional memory (G06F9/528 takes precedence)}
- G06F 12/0815: Cache consistency protocols
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
- G06F 12/1491: {in a hierarchical protection system, e.g. privilege levels, memory rings}
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.

## Claims

### Claim 1

A computer-implemented method comprising, in a transactional memory environment comprising a plurality of processors:
identifying one or more coherence privilege state indicators, said coherence privilege state indicators (i) being associated with said one or more selected processors, (ii) indicate a level of privilege associated with the one or more selected processors for coherence control interactions with other processors, and (iii) have at least three possible settings with at least one setting being based on a priority of said one or more selected processors;
determining a coherence privilege behavioral pattern for said one or more selected processors based on said one or more coherence privilege state indicators, wherein the coherence privilege behavioral pattern (i) is based on the level of privilege and (ii) includes at least three sets of rules that respectively govern, at least in part, how transactions are processed by said one or more selected processors during at least three sequential time periods of operation for said one or more selected processors; and
processing a transaction by said one or more selected processors based, at least in part, on the coherence privilege behavioral pattern.

### Claim 2 (depends on 1)

The computer-implemented method of claim 1, further comprising:
receiving a coherence conflict indication, said coherence conflict indication caused to be sent by one or more requesting parties;
determining a coherence response based on said coherence privilege behavioral pattern; and
communicating a coherence response indication comprising said coherence response to a recipient group comprising said one or more requesting parties.

### Claim 3 (depends on 2)

The computer-implemented method of claim 2, wherein:
said coherence conflict indication comprises one or more identifying markers; and
said coherence response indication comprises an indication of said one or more identifying markers.

### Claim 4 (depends on 1)

The computer-implemented method of claim 1, further comprising:
receiving a coherence privilege modification indication, said coherence privilege modification indication denoting a request for change in said one or more coherence privilege state indicators; and
determining whether to approve said coherence privilege modification indication based on one or more coherence privilege guidelines.

### Claim 5 (depends on 1)

The computer-implemented method of claim 1, wherein said one or more coherence privilege state indicators are in a state selected from the group consisting of a regular state and a super-core state.

### Claim 6 (depends on 5)

The computer-implemented method of claim 5, wherein determining said coherence privilege behavioral pattern comprises:
receiving a coherence conflict indication, said coherence conflict indication caused to be sent by one or more requesting parties;
aborting a transaction being executed by said one or more selected processors if said one or more coherence privilege state indicators are in a regular state; and
refusing to abort said transaction if said one or more coherence privilege state indicators are in a super-core state.

### Claim 7 (depends on 1)

The computer-implemented method of claim 1, wherein said transactional memory environment is characterized by a behavior that a transactional abort is triggered by a conflict trigger action as to a conflict transaction including a conflict read-set and a conflict write-set, said conflict trigger action being selected from the group consisting of:
any of said plurality of processors storing to either said conflict read-set or said conflict write-set; and
any of said plurality of processors loading from said conflict write-set.