# US 10,120,799 B2 · Electronic device and method for fabricating the same

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- Number: US 10,120,799 B2
- Document ID: US10120799B2
- Status: Granted
- Kind: B2
- Application number: 15/675,585
- Filed: 2017-08-11
- Published: 2017-11-30
- Granted: 2018-11-06
- Earliest claimed: 2014-12-17
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Cha-Deok Dong; Ki-Seon Park; Bo-Mi Lee; Won-Joon Choi; Guk-Cheon Kim; Yang-Kon Kim
- Web page: https://patentgrep.com/patent/US10120799B2

## CPC

- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/10: Magnetoresistive devices
- H10N 50/85: Materials of the active region
- G06F 2212/1028: Power efficiency
- G06F 2212/202: Non-volatile memory
- G06F 2212/222: Non-volatile memory
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

## Claims

### Claim 1

A method for fabricating an electronic device comprising a semiconductor memory, comprising:
providing a substrate in which a first region and a second region are defined;
forming an interlayer dielectric layer having a first conductive pattern and a second conductive pattern, over the substrate, wherein the first conductive pattern is located at the first region and has a planarized top surface with the interlayer dielectric layer, and the second conductive pattern is located at the second region and includes at least a portion recessed below a top surface of the interlayer dielectric layer;
forming a variable resistance layer over the interlayer dielectric layer to cover the first conductive pattern and the second conductive pattern;
forming a capping layer including a non-metallic material which prevents a penetration of a wet chemical, over the variable resistance layer;
forming a mold layer over the capping layer;
forming a hard mask pattern in a portion of the mold layer corresponding to the first region;
removing at least a portion of the mold layer; and
etching the capping layer and the variable resistance layer using the hard mask pattern.

### Claim 2 (depends on 1)

The method of claim 1, wherein the capping layer includes an amorphous semiconductor material, a silicon nitride, a silicon oxynitride, a metal oxide or a metal nitride.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming of the capping layer comprising:
forming a metallic layer over the variable resistance layer; and
oxidizing at least an upper portion of the metallic layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the oxidizing of the metallic layer includes converting the metallic layer to include non-metallic material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming of the capping layer comprising:
forming a metallic layer over the variable resistance layer; and
nitrifying at least an upper portion of the metallic layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the nitrifying of the metallic layer includes converting the metallic layer to include non-metallic material.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming of the capping layer is performed at a temperature of 300° C. or less.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first region includes a memory cell array region and the second region includes a peripheral circuit region.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first region includes a memory cell array region and the second region includes a vernier key region.

### Claim 10 (depends on 9)

The method of claim 9, wherein, at a time that the mold layer of the first region is removed, a portion of the mold layer of the second region remains and a hard mask material including a same material as the hard mask pattern adheres to the portion of the mold layer of the second region.

### Claim 11 (depends on 1)

The method of claim 1, wherein the variable resistance layer includes an MTJ (Magnetic Tunnel Junction) structure.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
forming an additional conductive pattern penetrating through the capping layer to be coupled to a top surface of the variable resistance layer, after the etching of the capping layer and the variable resistance layer.

### Claim 13 (depends on 1)

The method of claim 1, wherein the substrate further defines a third region different from the first and second regions, and wherein:
the interlayer dielectric layer further includes a third conductive pattern located over the third region of the substrate,
at least a portion of the third conductive pattern is recessed below the top surface of the interlayer dielectric layer, and
a width and a depth of the recessed portion of the third conductive pattern are greater than a width and a depth of the recessed portion of the second conductive pattern.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first region includes a memory cell array region, the second region includes a peripheral circuit region, and the third region includes a vernier key region.

### Claim 15 (depends on 1)

The method of claim 1, wherein the first conductive pattern has a width smaller than the second conductive pattern.

### Claim 16 (depends on 1)

The method of claim 1, wherein the capping layer has a thickness between 50 Å and 150 Å.

### Claim 17 (depends on 1)

The method of claim 1, wherein the hard mask pattern includes material having an etch rate different from those of the capping layer and the mold layer.

### Claim 18 (depends on 1)

The method of claim 1, further comprising forming a spacer layer to surround the variable resistance layer, the spacer layer including an insulating material.

### Claim 19 (depends on 1)

The method of claim 1, wherein the forming of the capping layer includes forming the capping layer to include non-metallic material.