# US 10,120,754 B2 · Data storage error protection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,754 B2 - Document ID: US10120754B2 - Status: Granted - Kind: B2 - Application number: 15/664,589 - Filed: 2017-07-31 - Published: 2017-11-16 - Granted: 2018-11-06 - Earliest claimed: 2015-06-10 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Paolo Amato; Marco Sforzin - Web page: https://patentgrep.com/patent/US10120754B2 ## CPC - G06F 11/1072: {in multilevel memories} - G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - H03M 13/00: Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes (error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C) - H03M 13/098: {using single parity bit} - H03M 13/2918: {with error correction codes in three or more dimensions, e.g. 3-dimensional product code where the bits are arranged in a cube} - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension. ## Claims ### Claim 1 An apparatus, comprising: an array of memory cells arranged in a first dimension and a second dimension; and a controller configured to: determine a set of symbols oriented obliquely to the first and second dimensions and corresponding to data stored in the memory cells; add subsets of the set of symbols to determine a number of parity check symbols; selectably protect, based on a same number of parity check symbols for each, a first subset of memory cells oriented parallel to the first dimension and a second subset of memory cells oriented parallel to the second dimension; and selectably recover a data storage error for a pillar or a tier of a three-dimensional (3D) array of memory cells based on the same number of parity check symbols used for recovery of the pillar and the tier. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the apparatus is further configured to: selectably recover the data storage error based on the same number of parity check symbols for either: the first subset of memory cells oriented parallel to the first dimension; or the second subset of memory cells oriented parallel to the second dimension. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the first subset of memory cells is a column of memory cells and the second subset of memory cells is a row of memory cells in a two-dimensional (2D) plane of the array. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first subset of memory cells is a pillar of memory cells and the second subset of memory cells is a tier of memory cells in a three-dimensional (3D) array of memory cells. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the apparatus is further configured to store the parity check symbols in a parity check tier in a three-dimensional (3D) array of memory cells. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the apparatus is further configured to store the parity check symbols as a parity check tier in memory coupled to a three-dimensional (3D) array of memory cells. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the apparatus is further configured to include a single set of parity check symbols that enables selectable performance of either an error recovery operation for a pillar or an error recovery operation for a tier of a three-dimensional (3D) array of memory cells. ### Claim 8 An apparatus, comprising: a three-dimensional (3D) array of memory cells; and a controller configured to: selectably perform, based on a same number of parity check symbols for each, an error recovery operation for a data storage error in at least one of a pillar of memory cells and a tier of memory cells of the 3D array; and recover the data storage error with an operation performed on symbols corresponding to obliquely oriented data sequences stored in successive tiers of the 3D array; wherein the operation includes storage of symbols for the obliquely oriented data sequences in a tier of parity check symbols. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the apparatus is further configured to selectably recover a data value or corresponding symbol for a single data storage error for the at least one of the pillar of memory cells and the tier of memory cells. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the apparatus is further configured to selectably recover all the data values or corresponding symbols for the at least one of the pillar of memory cells and the tier of memory cells with the data storage error. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein the apparatus is further configured to: recover the data storage error for a pillar of memory cells with an XOR operation performed on symbols corresponding to obliquely oriented data sequences stored with a cyclic shift operation; and wherein the XOR operation is performed on symbols corresponding to a subset of the symbols in each successive tier of the 3D array that includes the tier of parity check symbols. ### Claim 12 An apparatus, comprising: a three-dimensional (3D) array of memory cells; and a controller configured to: determine a set of symbols corresponding to data stored in the 3D array with a cyclic shift operation as obliquely oriented in successive tiers of the 3D array; add subsets of symbols to determine a number of parity check symbols; and perform an error recovery operation for a data storage error in at least one of a pillar and a tier of the 3D array based on a stored set of parity check symbols selectably usable for error recovery operations for both the pillar and the tier. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the successive tiers include a tier for the stored set of parity check symbols. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the apparatus is further configured to determine the stored set of parity check symbols by exclusive or (XOR) addition of symbols from successive tiers for sequences of obliquely oriented cyclic shifted data. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the apparatus is further configured to recover the data storage error with an exclusive or (XOR) operation performed on a sequence of symbols corresponding to obliquely oriented data stored with the cyclic shift operation in successive tiers of the 3D array and in a single stored set of parity check symbols. ### Claim 16 (depends on 12) The apparatus of claim 12, wherein the apparatus is further configured to determine a single stored set of parity check symbols selectably usable for error recovery operations for both the pillar and the tier. ### Claim 17 (depends on 12) The apparatus of claim 12, wherein the apparatus is further configured to selectably recover the data storage error for a pillar or a tier of the 3D array of memory cells based on use of a single stored set of parity check symbols. ### Claim 18 (depends on 12) The apparatus of claim 12, wherein the apparatus is further configured to: recover the data storage error for a pillar of memory cells with an exclusive or (XOR) operation performed on symbols corresponding to obliquely oriented data stored with a cyclic shift operation; and wherein the symbols correspond to a subset of the symbols in each successive tier of the 3D array that includes a single stored set of parity check symbols. ### Claim 19 (depends on 12) The apparatus of claim 12, wherein the apparatus is further configured to perform an error detection operation to determine a location of a data storage error by sensing data stored in the memory cells of the 3D array.