# US 10,120,750 B2 · Cache memory, error correction circuitry, and processor system

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- Number: US 10,120,750 B2
- Document ID: US10120750B2
- Status: Granted
- Kind: B2
- Application number: 15/262,241
- Filed: 2016-09-12
- Published: 2016-12-29
- Granted: 2018-11-06
- Earliest claimed: 2014-03-18
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Susumu Takeda; Hiroki Noguchi; Kazutaka Ikegami; Shinobu Fujita
- Web page: https://patentgrep.com/patent/US10120750B2

## CPC

- G06F 11/1064: {in cache or content addressable memories}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0893: Caches characterised by their organisation or structure
- G06F 12/16: Protection against loss of memory contents {(contains no material, see G06F11/00)}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1024: Latency reduction
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/283: Plural cache memories
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A cache memory includes cache memory circuitry that is accessible per cache line and a redundant-code storage that stores one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line and one or more numbers of second redundant codes to be used for error detection of a part of the cache line data.

## Claims

### Claim 1

A cache memory comprising:
cache memory circuitry that is accessible per cache line; and a redundant-code storage that stores:
one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line, one or more numbers of second redundant codes to be used for error detection of critical data included in a part of the cache line data, and identification information to identify data corresponding to the second redundant codes, wherein the critical data comprises at least one of data corresponding to an address in a head side of the cache line, data accessed recently by a processor in the cache line, and a part of data selected in descending order of being more recently accessed by the processor core in the cache line.

### Claim 2 (depends on 1)

The cache memory of claim 1, wherein the second redundant codes are used for error detection and correction of data having a length equal to integral multiple of a length of word data included in the corresponding cache line data.

### Claim 3 (depends on 1)

The cache memory of claim 1, wherein the cache memory circuitry comprises:
a data cache that stores the cache line data; and
a tag that stores address information on the cache line data stored in the data cache, wherein the redundant-code storage is provided at a part of the data cache or the tag.

### Claim 4 (depends on 1)

The cache memory of claim 1, wherein the cache memory circuitry comprises:
a data cache that stores the cache line data; and
a tag that stores address information on the cache line data stored in the data cache, wherein the redundant-code storage is provided at a part of the tag.

### Claim 5 (depends on 3)

The cache memory of claim 3, wherein the data cache includes a non-volatile memory; and the tag includes a volatile memory.

### Claim 6 (depends on 3)

The cache memory of claim 3, wherein the data cache includes an MRAM (Magnetoresistive RAM); and the tag includes an SRAM (Static RAM).

### Claim 7 (depends on 3)

The cache memory of claim 3, wherein the data cache has a plurality of ways accessible per cache line, wherein the redundant-code storage stores, for a way, a same number of the second redundant codes.

### Claim 8 (depends on 3)

The cache memory of claim 3, wherein the data cache has a plurality of ways accessible per cache line, wherein the redundant-code storage stores different numbers of the second redundant codes in at least two ways among the plurality of ways.

### Claim 9 (depends on 8)

The cache memory of claim 8, wherein the redundant-code storage stores a more number of the second redundant codes for a way which is accessed at a higher frequency in the data cache.

### Claim 10 (depends on 3)

The cache memory of claim 3, wherein the redundant-code storage stores at least the one second redundant code which corresponds to an address of data stored in the data cache, in descending order from most recently accessed data.

### Claim 11 (depends on 3)

The cache memory of claim 3, wherein the redundant-code storage stores at least the one second redundant code which corresponds to a head side address in the cache line of the data cache.

### Claim 12 (depends on 3)

The cache memory of claim 3, wherein the redundant-code storage stores by priority, the second redundant code corresponding to data accessed by a processor at a higher frequency among data stored in the data cache.

### Claim 13 (depends on 1)

The cache memory of claim 1 further comprising a cache controller to control access to the cache memory and the redundant-code storage, wherein the cache controller controls so that the first and second redundant codes are stored in the redundant-code storage in parallel.

### Claim 14 (depends on 1)

The cache memory of claim 1 further comprising a cache controller to control access to the cache memory and the redundant-code storage, wherein the cache controller controls so that the first and second redundant codes are stored in the redundant-code storage one after another.

### Claim 15 (depends on 1)

The cache memory of claim 1 further comprising a cache controller to control access to the cache memory and the redundant-code storage, wherein, the cache controller updates the second redundant codes in the redundant-code storage if there is a change in the part of the cache line data when updating cache line data.

### Claim 16

An error correction circuitry comprising:
error correction circuitry to perform error correction per cache line based on a first redundant code corresponding to cache line data stored in a cache memory per cache line; and error detection circuitry to perform error detection of the critical data based on a second redundant code corresponding to the critical data included in a part of the cache line data, wherein the critical data comprises at least one of data corresponding to an address in a head side of the cache line, data accessed recently by a processor in the cache line, and a part of data selected in descending order of being more recently accessed by the processor core in the cache line.

### Claim 17 (depends on 16)

The error correction circuitry of claim 16 further comprising a data transfer controller to transfer data error-detected by the error detection circuitry to a processor core before completion of the error correction by the error correction circuitry.

### Claim 18

A processor system comprising:
a processor core;
a first-level cache memory; and
a layered cache memory than the first-level cache memory,
wherein the layered cache memory comprises:
a data cache;
a tag that stores address information on data stored in the data cache; and
a redundant-code storage that stores a first redundant code used for error correction of cache line data stored in the data cache per cache line, a second redundant code to be used for error detection of critical data included in a part of the cache line data, and identification information to identify data corresponding to the second redundant codes,
wherein the critical data comprises at least one of data corresponding to an address in a head side of the cache line, data accessed recently by a processor in the cache line, and a part of data selected in descending order of being more recently accessed by the processor core in the cache line.

### Claim 19 (depends on 18)

The processor system of claim 18 further comprising:
error correction circuitry to perform error correction per cache line based on the first redundant code;
error detection circuitry to perform error detection of the critical data based on the second redundant code corresponding to the critical data included in a part of the cache line data; and
a data transfer controller to transfer data error-detected by the error detection circuitry to the processor core before completion of the error correction by the error correction circuitry.