# US 10,120,749 B2 · Extended application of error checking and correction code in memory

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- Number: US 10,120,749 B2
- Document ID: US10120749B2
- Status: Granted
- Kind: B2
- Application number: 15/282,793
- Filed: 2016-09-30
- Published: 2018-04-05
- Granted: 2018-11-06
- Earliest claimed: 2016-09-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Pete D. Vogt
- Web page: https://patentgrep.com/patent/US10120749B2

## CPC

- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

ECC (error checking and correction) can be extended to allow an ECC code to correct memory subarray errors. A memory device includes multiple input/output (I/O) connectors to interface with an external device such as a controller. The memory device includes multiple arrays or subarrays that are specifically mapped to I/O connectors instead of arbitrarily routed. As such, the data paths of the memory subarrays can be exclusively routed to a specific I/O connector. The I/O connector can be uniquely associated with a single memory subarray, or multiple memory subarrays can be mapped to a specific I/O connector. The mapping is in accordance with an error checking and correcting (ECC) code matrix, where a code of the ECC code matrix corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the associated one or multiple memory subarrays.

## Claims

### Claim 1

A memory device, comprising:
multiple input/output (I/O) connectors to interface the memory device to an external device;
a memory array, including multiple subarrays each including multiple rows of memory cells; and
a data path including one or more signal lines to couple the memory array to the I/O connectors, wherein the data path is to route all data between a memory subarray and a specific I/O connector in accordance with an error checking and correcting (ECC) code matrix, where a code of the ECC code matrix corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the memory subarray.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the memory device comprises an in-package memory device of a system-on-a-chip including a processor die.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the memory device comprises a dynamic random access memory (DRAM) die.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the multiple I/O connectors comprise an 18-bit data interface.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the multiple I/O connectors comprise a 36-bit data interface.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the memory subarray comprises a subarray of a bank of the memory device.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the data path is to map a single memory subarray to a specific I/O connector.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the data path is to map multiple memory subarrays to a specific I/O connector.

### Claim 9 (depends on 1)

The memory device of claim 1, further comprising:
a multiplexer to multiplex multiple data signal lines between the memory subarray and the specific I/O connector.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein all data signal lines of the memory subarray route to a single multiplexer.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the data path is to route a burst of data bits from the memory subarray to the specific I/O connector over multiple transfer cycles.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein the data path is to route data from the specific I/O connector to the memory subarray for a write operation.

### Claim 13 (depends on 1)

The memory device of claim 1, wherein the data path is to route data to the specific I/O connector from the memory subarray for a read operation.

### Claim 14

A system on a chip, comprising:
a processor die on a substrate; and
an in-package dynamic random access memory (DRAM) device coupled to the processor die via the substrate, the DRAM device including
multiple input/output (I/O) connectors to interface the DRAM device to the processor die;
a memory bank including multiple subarrays having multiple rows of memory cells; and
multiple data paths including one or more signal lines to couple the subarrays to the I/O connectors, wherein a data path is to route all data between a specific subarray and a specific I/O connector in accordance with an error checking and correcting (ECC) code matrix, where a code of the ECC code matrix corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the specific subarray.

### Claim 15 (depends on 14)

The system of claim 14, wherein the multiple I/O connectors comprise an 18-bit or a 36-bit data interface.

### Claim 16 (depends on 14)

The system of claim 14, wherein the data path is to map a single subarray exclusively to the specific I/O connector.

### Claim 17 (depends on 14)

The system of claim 14, wherein the data path is to map multiple subarrays exclusively to the specific I/O connector.

### Claim 18 (depends on 14)

The system of claim 14, wherein the data path is to route data from the specific I/O connector to the specific memory subarray for a write operation, and to route data to the specific I/O connector from the specific memory subarray for a read operation.

### Claim 19 (depends on 14)

The system of claim 14, further comprising one or more of:
a memory controller on the processor die;
a display communicatively coupled to the processor die;
a battery to power the system; or
a network interface communicatively coupled to the processor die.

### Claim 20

A method for input/output (I/O) with a memory device, comprising:
associating a memory subarray of the memory device with a specific one of multiple I/O connectors of the memory device, wherein a bit of an ECC code corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the associated memory subarray; and
routing all I/O data signal lines between the specific I/O connector and the memory subarray.

### Claim 21 (depends on 20)

The method of claim 20, wherein the memory subarray comprises a subarray of a bank of a dynamic random access memory (DRAM) die.

### Claim 22 (depends on 20)

The method of claim 20, wherein routing the I/O data signal lines between the specific I/O connector and the memory subarray comprises routing the I/O data signal lines through a multiplexer to map all I/O data signal lines to the specific I/O connector.

### Claim 23 (depends on 22)

The method of claim 22, wherein routing the I/O data signal lines through the multiplexer comprises routing the I/O data signal lines of multiple memory subarrays through the multiplexer to the specific I/O connector.