# US 10,120,740 B2 · Apparatus and methods for debugging on a memory device

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- Number: US 10,120,740 B2
- Document ID: US10120740B2
- Status: Granted
- Kind: B2
- Application number: 15/077,318
- Filed: 2016-03-22
- Published: 2017-09-28
- Granted: 2018-11-06
- Earliest claimed: 2016-03-22
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Perry V. Lea; Shawn Rosti
- Web page: https://patentgrep.com/patent/US10120740B2

## CPC

- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/0778: {Dumping, i.e. gathering error/state information after a fault for later diagnosis}
- G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)}
- G06F 11/364: {tracing values on a bus}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1036: {using data shift registers}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/408: Address circuits
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation
- G11C 2207/2245: Memory devices with an internal cache buffer
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

## Claims

### Claim 1

An apparatus, comprising:
a memory device, comprising:
an array of memory cells;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and
a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:
store debugging code in the array of memory cells;
execute instructions to perform logical operations using the sensing circuitry, wherein the instructions to perform the logical operations are stored in the array of memory cells; and
receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the indication is stored within the instructions to perform the logical operations.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the array of memory cells are dynamic random access memory (DRAM) cells.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the controller is configured to use a DRAM protocol and DRAM logical and electrical interfaces to execute the debugging code in the memory device.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to receive the instructions pre-resolved by the host.

### Claim 5

An apparatus, comprising:
a memory device, comprising:
an array of memory cells;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and
a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:
store microcode instructions containing debugging code in the array of memory cells;
execute microcode instructions to perform logical operations using the sensing circuitry; and
detect one or more bits in the executing microcode instructions to halt a logical operation and perform a debugging routine according to the debugging code on the memory device.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein:
a bank arbiter is coupled to a plurality of banks in the memory device; and each bank of the plurality of banks includes a memory controller configured to:
receive an instruction block of microcode instructions relevant to a particular bank from the bank arbiter; and
store instructions in the received instruction block to a plurality of locations for the particular bank as allocated by the host.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein each memory controller is configured to:
receive instructions to start execution of the instruction block;
retrieve instructions from a plurality of locations for a bank of the memory die as needed to handle branches, loops, logical and data operations contained within the instruction block;
cache retrieved instructions local to the bank; and
re-cache retrieved instructions as needed.

### Claim 8 (depends on 5)

The apparatus of claim 5, wherein:
the apparatus further includes logic circuitry coupled to the sensing circuitry, the logic circuitry including latches in the form of sense amplifiers; and
wherein the memory controller is configured to cache and re-cache retrieved instructions to the logic circuitry.

### Claim 9 (depends on 5)

The apparatus of claim 5, wherein:
the apparatus comprises a plurality of memory device, each memory device of the plurality of memory device having a bank arbiter configured to couple to a channel controller via an interface; and
wherein the channel controller is configured to dispatch instruction blocks to each bank arbiter for each of the plurality of memory device.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the apparatus is configured to:
receive a subsequent instruction block of microcode instructions to a bank of a respective memory device via a respective bank arbiter;
store instructions in the subsequent received instruction block to a plurality of locations for the bank while the memory controller is executing a previously received instruction block; and
start of future calculations by the compute component.

### Claim 11

An apparatus, comprising:
a memory device having a bank arbiter coupled to a plurality of memory banks, the bank arbiter to dispatch microcode instructions to the plurality of banks, wherein each bank of the plurality of banks comprises:
an array of memory cells;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations; and
a controller coupled to the array and the sensing circuitry, wherein the controller is configured to:
store debugging code in the array of memory cells;
execute instructions to perform logical operations using the sensing circuitry; and
receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the apparatus is configured to:
receive an instruction block of microcode instructions relevant to the bank arbiter from a channel controller; and
store instructions in the received instruction block to a plurality of locations in the array as allocated by the channel controller.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein:
the array of memory cells is a dynamic random access memory (DRAM) array of memory cells; and
the controller is configured to use a DRAM protocol and DRAM logical and electrical interfaces to:
receive the microcode instructions from the channel controller via the bank arbiter; and
route the microcode instructions to the compute component.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the controller comprises:
control logic;
a sequencer; and
timing circuitry.

### Claim 15 (depends on 11)

The apparatus of claim 11, wherein the control state machine is configured to:
retrieve the instructions from a dynamic random access memory (DRAM) array on the memory device; and
decode the instructions into microcode operations to be implemented by the sequencer.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the sequencer is configured to:
generate sequences of operations for the DRAM array on the memory device, the sequences of operations comprising logical operations using the sensing circuitry; and
wherein the sequences of operations include halting the logical operation and executing the debugging code on the memory device upon receipt of the indication by the sequencer.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein timing circuitry is configured to provide conflict free access to the DRAM array from a plurality of first in first out (FIFO) queues.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the plurality of FIFO queues comprises:
an array computation FIFO;
an instruction fetch FIFO;
a microcode fetch FIFO; and
an array input/output (I/O) FIFO.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein the control state machine and the sequencer are configured to:
generate status information;
route the status information to the bank arbiter via a status interface; and
wherein the bank arbiter is configured to:
aggregate the status information; and
report the status information to a channel controller via an out of bound bus.

### Claim 20

A method for debugging on a memory device, comprising:
storing microcode instructions containing debugging code in an array of memory cells;
receiving microcode instructions to a controller on the memory device to perform logical operation;
detecting an indication in the received microcode instructions to halt a logical operation and to perform a debugging routine according to the debugging; and
executing microcode instructions on the memory device using sensing circuitry having a sense amplifier and a compute component to perform the logical operations.

### Claim 21 (depends on 20)

The method of claim 20, wherein the method comprises:
storing the microcode instructions in a dynamic random access memory (DRAM) array of a processing in memory (PIM) device using the controller on the memory device.

### Claim 22 (depends on 20)

The method of claim 20, wherein the method comprises performing a single step debugging operation according to the debug code to step to a next microcode instruction.

### Claim 23 (depends on 20)

The method of claim 20, wherein the method comprises performing a step over debugging operation according to the debug code to step over a next microcode instruction and to continue a perform a debugging routine on a subsequent microcode instruction.

### Claim 24

An apparatus, comprising:
a memory device, comprising:
an array of memory cells;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and
a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:
store debugging code in the array of memory cells;
execute instructions to perform logical operations using the sensing circuitry, wherein the instructions to perform the logical operations are stored in the array of memory cells; and
receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the indication is a bit stored within the instructions to cause the controller to halt the logical operation.

### Claim 25

An apparatus, comprising:
a memory device, comprising:
an array of memory cells;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and
a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:
store debugging code in the array of memory cells;
execute instructions to perform logical operations using the sensing circuitry, wherein the instructions to perform the logical operations are stored in the array of memory cells; and
receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the indication is stored within the instructions to perform the logical operations; and
the indication is configured to cause the controller to;
pause execution of a logical operation; and
continue the logical operation according to the debugging code.

### Claim 26 (depends on 25)

The apparatus of claim 25, wherein the debugging code comprises instructions to cause the memory device to continue the logical operation while executing a debugging step operation.

### Claim 27 (depends on 25)

The apparatus of claim 25, wherein the debugging code comprises instructions to cause the memory device to continue the logical operation while executing a single step debugging operation.

### Claim 28 (depends on 25)

The apparatus of claim 25, wherein the debugging code comprises instructions to cause the memory device to continue the logical operation while executing a step over debugging operation.

### Claim 29

An apparatus, comprising:
a memory device, comprising:
an array of memory cells;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component configured to perform logical operations on the memory device; and
a controller coupled to the array and sensing circuitry, the controller configured to cause the memory device to:
store debugging code in the array of memory cells;
execute instructions to perform logical operations using the sensing circuitry; and
receive an indication in the executing instructions to halt a logical operation and to execute the debugging code on the memory device, wherein the instructions are microcode instructions, and wherein the debugging code and the indication are contained in the microcode instructions.

### Claim 30

A method for debugging on a memory device, comprising:
storing microcode instructions containing debugging code in an array of memory cells;
receiving microcode instructions to a controller on the memory device to perform logical operations,
detecting an indication in the received microcode instructions to halt a logical operation and to perform a debugging routine according to the debugging, wherein detecting the indication in the microcode instructions comprises detecting one or more set bits in the received microcode instructions to halt the logical operation and perform the debugging routine.

### Claim 31 (depends on 30)

The method of claim 30, wherein detecting the one or more set bits comprises:
using a sequencer in the controller to identify a set debug bit in the microcode instructions; and
stopping a program counter and not allowing new instructions to execute.

### Claim 32

A method for debugging on a memory device, comprising:
storing microcode instructions containing debugging code in an array of memory cells;
receiving microcode instructions to a controller on the memory device to perform logical operations;
detecting an indication in the received microcode instructions to halt a logical operation and to perform a debugging routine according to the debugging; and
setting a debug bit in the microcode instructions programmatically after the microcode instructions are stored on the memory device.

### Claim 33

A method for debugging on a memory device, comprising:
storing microcode instructions containing debugging code in an array of memory cells;
receiving microcode instructions to a controller on the memory device to perform logical operations,
detecting an indication in the received microcode instructions to halt a logical operation and to perform a debugging routine according to the debugging,
executing microcode instructions on the memory device using sensing circuitry having a sense amplifier and a compute component to perform the logical operations, wherein the executing microcode instructions on the memory device includes executing the microcode instructions on a processing in memory (PIM) device; and
using sensing circuitry on the PIM device to:
perform logical functions including AND, OR, NOT, XOR, NAND, and NOR logical functions; and
non-Boolean logic operations including copy, compare and erase.

### Claim 34 (depends on 33)

The method of claim 33, wherein the method comprises storing the microcode instructions to a plurality of subarrays in a dynamic random access memory (DRAM) on the PIM.