# US 10,120,737 B2 · Apparatus for detecting bugs in logic-based processing devices

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- Number: US 10,120,737 B2
- Document ID: US10120737B2
- Status: Granted
- Kind: B2
- Application number: 15/047,376
- Filed: 2016-02-18
- Published: 2016-08-25
- Granted: 2018-11-06
- Earliest claimed: 2015-02-19
- Assignees: The Board of Trustees of the Leland Stanford Junior University
- Applicants: The Board of Trustees of the Leland Stanford Junior University
- Inventors: Hai Lin; Subhasish Mitra
- Web page: https://patentgrep.com/patent/US10120737B2

## CPC

- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G01R 31/31705: {Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544)}
- G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An apparatus for detecting bugs in a logic-based processing device during post-silicon validation is disclosed. The apparatus includes a test bench and a Proactive Load and Check (PLC) hardware checker inserted within an uncore component of the logic-based processing device. The test bench includes a processor for converting an original test program to a modified test program for validating the functionalities of the logic-based processing device during post-silicon validation. The PLC hardware checker includes a controller, an address generator, a data register and a comparator.

## Claims

### Claim 1

An apparatus for detecting bugs in a logic-based processing device during post-silicon validation, said apparatus comprising:
a test bench having a processor for converting an original test program to a modified test program by dividing instructions of said original test program into multiple blocks of instructions, and by substituting an original register in one of said blocks of instructions with a shadow register, and for executing said modified test program; and
a plurality of Proactive Load and Check (PLC) hardware checkers, each inserted within an uncore component of said logic-based processing device to be tested, wherein said PLC hardware checkers perform PLC operations concurrently, wherein one of said PLC hardware checkers includes:
a controller for initiating a PLC operation in response to a determination that a predetermined set of criteria has been met;
an address generator for generating an address of an original variable in said uncore component with which said PLC hardware checker is associate;
a data register for storing a value at said original variable address: and
a comparator for comparing said value stored within said data register to a value at a corresponding variable address within said modified test program, and for indicating an existence of a bug within said logic-based processing device to be tested when said value stored within said data register does not match said value from said corresponding variable address within said modified test program.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein said predetermined set of criteria includes no load/store operation in progress in a cache memory.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein said predetermined set of criteria includes less than a predetermined number of PLC operation in progress.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein said predetermined set of criteria includes no PLC operation between a store operation to an original register and a corresponding store operation to said one shadow register within said modified test program.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein said processor adds a plurality of shadow instructions to said original test program in order to convert said original test program to said modified test program.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein said encore component is a cache memory.