# US 10,120,691 B2 · Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,691 B2 - Document ID: US10120691B2 - Status: Granted - Kind: B2 - Application number: 15/214,270 - Filed: 2016-07-19 - Published: 2016-11-10 - Granted: 2018-11-06 - Earliest claimed: 2016-07-19 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Boris Ginzburg; Ronny Ronen; Eliezer Weissmann; Karthikeyan Vaithianathan; Ehud Cohen - Web page: https://patentgrep.com/patent/US10120691B2 ## CPC - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3881: {Arrangements for communication of instructions and data} - G06F 9/461: {Saving or restoring of program or task context} - G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In one embodiment, a processor includes an accelerator, a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction, and an execution unit to execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator. ## Claims ### Claim 1 A processor comprising: a plurality of accelerators; a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction; and an execution unit to: execute the first decoded instruction to, for a thread executing on at least one accelerator of the plurality of accelerators that is to be placed in an inactive state, cause a save of context information for each of the at least one accelerator of the plurality of accelerators for the thread, and a save of a vector identifying the at least one accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine which of the plurality of accelerators have saved context information for the thread, read the saved context information, and restore the saved context information into the at least one accelerator. ### Claim 2 (depends on 1) The processor of claim 1, wherein the at least one accelerator is multiple accelerators and less than all of the plurality of accelerators. ### Claim 3 (depends on 1) The processor of claim 1, further comprising a register having fields to individually enable certain ones of the plurality of accelerators. ### Claim 4 (depends on 1) The processor of claim 1, wherein the at least one accelerator operates out of a same memory space as the execution unit. ### Claim 5 (depends on 1) The processor of claim 1, wherein the vector comprises a field to indicate an instruction set extension that is enabled for the thread. ### Claim 6 A method comprising: decoding a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction with a decoder of a processor; executing the first decoded instruction with an execution unit of the processor to, for a thread executing on at least one accelerator of a plurality of accelerators of the processor that is to be placed in an inactive state, cause a save of context information for each of the at least one accelerator of the plurality of accelerators for the thread, and a save of a vector identifying the at least one accelerator corresponding to the context information; and executing the second decoded instruction with the execution unit of the processor to read the vector to determine which of the plurality of accelerators have saved context information for the thread, read the saved context information, and restore the saved context information into the at least one accelerator. ### Claim 7 (depends on 6) The method of claim 6, wherein the at least one accelerator is multiple accelerators and less than all of the plurality of accelerators. ### Claim 8 (depends on 6) The method of claim 6, further comprising providing a register having fields to individually enable certain ones of the plurality of accelerators. ### Claim 9 (depends on 6) The method of claim 6, further comprising operating the at least one accelerator out of a same memory space as the execution unit. ### Claim 10 (depends on 6) The method of claim 6, wherein the vector comprises a field to indicate an instruction set extension that is enabled for the thread. ### Claim 11 A non-transitory machine readable medium containing program instructions that when processed by a processor cause a method to be performed, the method comprising: decoding a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction with a decoder of the processor; executing the first decoded instruction with an execution unit of the processor to, for a thread executing on at least one accelerator of a plurality of accelerators of the processor that is to be placed in an inactive state, cause a save of context information for each of the at least one accelerator of the plurality of accelerators for the thread, and a save of a vector identifying the at least one accelerator corresponding to the context information; and executing the second decoded instruction with the execution unit of the processor to read the vector to determine which of the plurality of accelerators have saved context information for the thread, read the saved context information, and restore the saved context information into the at least one accelerator. ### Claim 12 (depends on 11) The non-transitory machine readable medium of claim 11, wherein the at least one accelerator is multiple accelerators and less than all of the plurality of accelerators. ### Claim 13 (depends on 11) The non-transitory machine readable medium of claim 11, wherein the method further comprises providing a register having fields to individually enable certain ones of the plurality of accelerators. ### Claim 14 (depends on 11) The non-transitory machine readable medium of claim 11, wherein the method further comprises operating the at least one accelerator out of a same memory space as the execution unit. ### Claim 15 (depends on 11) The non-transitory machine readable medium of claim 11, wherein the vector comprises a field to indicate an instruction set extension that is enabled for the thread. ### Claim 16 A processor comprising: an accelerator; a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction; and an execution unit to: execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator. ### Claim 17 (depends on 16) The processor of claim 16, wherein the accelerator is multiple accelerators and less than all of a plurality of accelerators of the processor. ### Claim 18 (depends on 16) The processor of claim 16, further comprising a register having fields to individually enable certain ones of a plurality of accelerators of the processor that includes the accelerator. ### Claim 19 (depends on 16) The processor of claim 16, wherein the accelerator operates out of a same memory space as the execution unit. ### Claim 20 (depends on 16) The processor of claim 16, wherein the vector comprises a field to indicate an instruction set extension that is enabled for the thread.