# US 10,120,690 B1 · Reservation station early age indicator generation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,690 B1 - Document ID: US10120690B1 - Status: Granted - Kind: B1 - Application number: 15/181,183 - Filed: 2016-06-13 - Granted: 2018-11-06 - Earliest claimed: 2016-06-13 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Skanda K. Srinivasa; Jonathan Jay Tyler - Web page: https://patentgrep.com/patent/US10120690B1 ## CPC - G06F 1/14: Time supervision arrangements, e.g. real time clock - G06F 1/3243: {Power saving in microcontroller unit} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems, apparatuses, and methods for pre-computing early age indicators for a non-shifting reservation station. A reservation station may include a plurality of entries storing a plurality of instruction operations prior to issuance to an execution unit. The reservation station may include control logic for pre-computing early age indicators for specifying which entry of each adjacent pair of entries is the oldest ready instruction operation. The early age indicators may be routed through registers and then through additional levels of control logic for determining the oldest ready instruction operation in all of the entries of the reservation station. ## Claims ### Claim 1 A processor comprising: one or more execution units; a reservation station comprising a plurality of entries, wherein each entry is configured to store an instruction operation until being issued for execution by one of the one or more execution units; an age matrix for storing indications of a relative age of each instruction operation stored in the reservation station; and control logic configured to: determine in a first clock cycle a plurality of early age indicators for subsets of entries of the plurality of entries, wherein each early age indicator indicates which entry of a given subset has an oldest ready instruction operation; store the plurality of early age indicators in a plurality of registers during the first clock cycle; and access the plurality of registers to determine in a second clock cycle which entry of all entries in the reservation station has an oldest ready instruction operation without reconsidering entries which were excluded by the early age indicators. ### Claim 2 (depends on 1) The processor as recited in claim 1, wherein said early age indicators are determined based at least in part on indications from the age matrix generated in a clock cycle previous to the first clock cycle. ### Claim 3 (depends on 1) The processor as recited in claim 1, wherein the control logic is configured to determine the plurality of early age indicators based at least in part on status data from the first clock cycle, wherein the status data comprises one or more of ready indications, allocated indications, and valid indications. ### Claim 4 (depends on 1) The processor as recited in claim 1, wherein each of said subsets of entries comprise an adjacent pair of entries of the plurality of entries of the reservation station. ### Claim 5 (depends on 1) The processor as recited in claim 1, wherein the control logic is configured to determine, in the second clock cycle, the oldest ready instruction operation for all of the entries of the reservation station. ### Claim 6 (depends on 1) The processor as recited in claim 1, wherein the reservation station is further configured to select the oldest ready instruction operation from all of the entries of the reservation station for issuance to an execution unit. ### Claim 7 (depends on 1) The processor as recited in claim 1, wherein entries of the reservation station are randomly allocated. ### Claim 8 A method comprising: storing instruction operations in a plurality of entries of a reservation station of a processor until being issued for execution by one of the one or more execution units; and determining in a first clock cycle a plurality of early age indicators for subsets of entries of the plurality of entries, wherein each early age indicator indicates which entry of a given subset has an oldest ready instruction operation; and storing the plurality of early age indicators in a plurality of registers during the first clock cycle; accessing the plurality of registers to determine in a second clock cycle which entry of all entries in the reservation station has an oldest ready instruction operation without reconsidering entries which were excluded by the early age indicators. ### Claim 9 (depends on 8) The method as recited in claim 8, wherein said early age indicators are determined based at least in part on indications from an age matrix generated in a clock cycle previous to the first clock cycle. ### Claim 10 (depends on 8) The method as recited in claim 8, further comprising determining the plurality of early age indicators based at least in part on status data from the first clock cycle, wherein the status data comprises one or more of ready indications, allocated indications, and valid indications. ### Claim 11 (depends on 8) The method as recited in claim 8, wherein each of said subsets of entries comprise an adjacent pair of entries of the plurality of entries of the reservation station. ### Claim 12 (depends on 8) The method as recited in claim 8, further comprising determining, in the second clock cycle, the oldest ready instruction operation for all of the entries of the reservation station. ### Claim 13 (depends on 8) The method as recited in claim 8, further comprising selecting the oldest ready instruction from all of the entries of the reservation station for issuance to an execution unit. ### Claim 14 (depends on 8) The method as recited in claim 8, further comprising randomly allocating entries of the reservation station. ### Claim 15 A computing system comprising: a memory; and a processor comprising: an execution unit; a dispatch unit; and a reservation station comprising: a plurality of entries, each of the plurality of entries being configured to store an instruction operation prior to issuance to an execution unit; control logic configured to: determine in a first clock cycle a plurality of early age indicators for subsets of entries of the plurality of entries, wherein each early age indicator indicates which entry of a given subset has an oldest ready instruction operation; store the plurality of early age indicators in a plurality of registers during the first clock cycle; access the plurality of registers to determine in a second clock cycle, based on the determined plurality of early age indicators which entry of all entries in the reservation station has an oldest ready instruction operation without reconsidering entries which were excluded by the early age indicators; wherein the reservation station is configured to keep each instruction operation in an entry into which the instruction operation was originally written until issuance to an execution unit; and wherein the dispatch unit is configured to write an instruction operation to any of the plurality of entries of the reservation station. ### Claim 16 (depends on 15) The computing system as recited in claim 15, wherein said early age indicators are determined based at least in part on indications from the age matrix generated in a clock cycle previous to the first clock cycle. ### Claim 17 (depends on 15) The computing system as recited in claim 15, wherein the control logic is configured to determine the plurality of early age indicators based at least in part on status data from the first clock cycle, wherein the status data comprises one or more of ready indications, allocated indications, and valid indications. ### Claim 18 (depends on 15) The computing system as recited in claim 15, wherein each of said subsets of entries comprise an adjacent pair of entries of the plurality of entries of the reservation station. ### Claim 19 (depends on 15) The computing system as recited in claim 15, wherein the control logic is configured to determine, in the second clock cycle, the oldest ready instruction operation for all of the entries of the reservation station. ### Claim 20 (depends on 15) The computing system as recited in claim 15, wherein entries of the reservation station are randomly allocated.