# US 10,120,687 B2 · Programmable controller

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- Number: US 10,120,687 B2
- Document ID: US10120687B2
- Status: Granted
- Kind: B2
- Application number: 14/629,528
- Filed: 2015-02-24
- Published: 2015-08-27
- Granted: 2018-11-06
- Earliest claimed: 2014-02-26
- Assignees: Fanuc Corporation
- Applicants: FANUC Corporation
- Inventors: Motoyoshi Miyachi; Yasushi Nomoto
- Web page: https://patentgrep.com/patent/US10120687B2

## CPC

- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30054: {Unconditional branch instructions}
- G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode}
- G06F 9/3804: {for branches, e.g. hedging, branch folding}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 2212/452: Instruction code
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A programmable controller for executing a sequence program comprises a processor for reading and executing an instruction code from an external memory, an instruction cache memory for storing a branch destination program code of a branch instruction included in the sequence program, and a cache controller for entering the branch destination program code in the instruction cache memory according to data on priority, the instruction code of the branch instruction including the data on priority of an entry into the instruction cache memory.

## Claims

### Claim 1

A programmable controller for executing a sequence program, the programmable controller comprising:
a processor for reading and executing an instruction code of a branch instruction from an external memory, the instruction code comprising a branch destination program code, the external memory being separate and distinct from the processor;
an instruction cache memory, separate and distinct from the processor, for storing the branch destination program code, the branch destination program code being entered into the instruction cache memory before the processor executes the instruction code; and
a cache controller for entering the branch destination program code in the instruction cache memory according to data on priority, the instruction code of the branch instruction including the data on priority of an entry into the instruction cache memory, wherein the data on priority indicates whether the branch destination program code is to be read from the external memory.

### Claim 2

A programmable controller for executing a sequence program, the programmable controller comprising:
a processor for reading and executing an instruction code of a branch instruction from an external memory, the instruction code comprising a branch destination program code, the external memory being separate and distinct from the processor;
an instruction cache memory, separate and distinct from the processor, for storing the branch destination program code, the branch destination program code being entered into the instruction cache memory before the processor executes the instruction code;
a counter for counting the number of executions of an individual branch instruction included in a sequence program while the sequence program is being executed; and
a cache line filing-away unit for entering branch destination program codes in the instruction cache memory in descending order of the number of executions,
wherein data on processing priority is added to each branch instruction code, the data on processing priority indicates whether the branch destination program code is to be read from the external memory.

### Claim 3 (depends on 2)

The programmable controller according to claim 2, wherein the data on processing priority is added to each branch instruction code according to the number of executions of an individual branch instruction included in the sequence program.

### Claim 4

A programmable controller for executing a sequence program, the programmable controller comprising:
a processor for reading and executing an instruction code of a branch instruction from an external memory, the instruction code comprising a branch destination program code, the external memory being separate and distinct from the processor;
an instruction cache memory, separate and distinct from the processor, for storing the branch destination program code, the branch destination program code being entered into the instruction cache memory before the processor executes the instruction code; and
a lock unit for, when all the entries in the instruction cache memory are filed away, preventing subsequent writing into the instruction cache memory,
wherein data on processing priority is added to each branch instruction, the data on processing priority indicates whether the branch destination program code is to be read from the external memory.