# US 10,120,684 B2 · Instructions and logic to perform mask load and store operations as sequential or one-at-a-time operations after exceptions and for un-cacheable type memory

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- Number: US 10,120,684 B2
- Document ID: US10120684B2
- Status: Granted
- Kind: B2
- Application number: 13/793,529
- Filed: 2013-03-11
- Published: 2013-07-25
- Granted: 2018-11-06
- Earliest claimed: 2007-12-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Doron Orenstien; Zeev Sperber; Robert Valentine; Benny Eitan
- Web page: https://patentgrep.com/patent/US10120684B2

## CPC

- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30018: {Bit or string instructions}
- G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3842: {Speculative instruction execution}
- G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)}
- G06F 15/8061: {Details on data memory access}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Logic is provided to receive and execute a mask move instruction to transfer unmasked data elements of a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. The logic is to execute a speculative full width operation, and if an exception occurs is to perform operations sequentially or one at a time. Other embodiments are described and claimed.

## Claims

### Claim 1

A processor comprising:
a decoder to decode a mask move instruction; and
an execution unit to execute the mask move instruction to transfer unmasked data elements of a vector data element that is to include a plurality of packed data elements from a source location to a destination location, wherein the mask move instruction is to be executed subject to mask information in a vector mask register and the mask information is to indicate which of the plurality of packed data elements of the vector data element are the unmasked data elements, wherein the execution unit is to issue a full width operation for the plurality of packed data elements of the vector data element, and, after and due to an exception that is to occur during the full width operation, is to perform an individual memory access operation, which is to access main memory, for each of the unmasked data elements one at a time.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the processor further comprises a memory subsystem having a store buffer including a plurality of entries each to store a pending instruction, a destination identifier, a source identifier, and mask information if the pending instruction to be stored in the entry is a mask store instruction.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the mask move instruction is a mask load instruction that is to include an opcode, a source identifier, and a destination identifier, and wherein the execution unit is to access the vector mask register responsive to the mask load instruction to obtain the mask information.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the execution unit is to access a first bit of each of a plurality of fields of the vector mask register to obtain the mask information, wherein each first bit is a mask value for a corresponding one of the plurality of packed data elements of the vector data element.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the mask move instruction is a mask load instruction, and the execution unit is to execute a speculative full width load operation as the full width operation to obtain and store the vector data element into a temporary storage and then determine that the exception occurred during the execution of the speculative full width load operation.

### Claim 6

A processor comprising:
a decoder to decode a mask move instruction; and
an execution unit to execute the mask move instruction to transfer unmasked data elements of a vector data element that is to include a plurality of packed data elements from a source location to a destination location, wherein the mask move instruction is to be executed subject to mask information in a vector mask register and the mask information is to indicate which of the plurality of packed data elements of the vector data element are the unmasked data elements, wherein the execution unit is to issue a full width operation for the plurality of packed data elements of the vector data element, and after an exception is to perform an individual operation for each of the unmasked data elements one at a time, wherein the mask move instruction is a mask load instruction, and the execution unit is to execute a speculative full width load operation as the full width operation to obtain and store the vector data element into a temporary storage and then determine that the exception occurred during the execution of the speculative full width load operation, and wherein the execution unit is to use a microcode handler to said perform the individual operation for said each of the unmasked data elements one at a time.

### Claim 7 (depends on 6)

The processor of claim 6, wherein the microcode handler is to determine if all of the mask information is of a second value.

### Claim 8

A processor comprising:
a decoder to decode a mask load instruction; and
an execution unit to execute the mask load instruction to load unmasked data elements of a vector data element that is to include a plurality of packed data elements from a source memory location to a destination register, wherein the mask load instruction is to be executed subject to mask information that is to indicate which of the plurality of packed data elements of the vector data element are the unmasked data elements, wherein the execution unit is to issue a full width load for the plurality of packed data elements of the vector data element, and when a type of memory for the full width load is un-cacheable the execution unit is to individually load each of the unmasked data elements one at a time.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the execution unit is to access a first bit of each of a plurality of fields of a vector mask register to obtain the mask information, wherein each first bit is to correspond to one of the plurality of packed data elements of the vector data element.